公开(公告)号：US11144458B2

公开(公告)日：2021-10-12

申请号：US15549284

申请日：2016-01-12

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Bruce James Mathewson ,  Matthew Lucien Evans

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/1009 ,  G06F12/10

Abstract: An apparatus (2) comprises processing circuitry (4) for performing data processing in response to instructions. The processing circuitry (4) supports a cache maintenance instruction (50) specifying a virtual page address (52) identifying a virtual page of a virtual address space. In response to the cache maintenance instruction, the processing circuitry (4) triggers at least one cache (18, 20, 22) to perform a cache maintenance operation on one or more cache lines for which a physical address of the data stored by the cache line is within a physical page that corresponds to the virtual page identified by the virtual page address provided by the cache maintenance instruction.

公开(公告)号：US11086659B2

公开(公告)日：2021-08-10

申请号：US16623569

申请日：2018-06-11

Applicant: ARM LIMITED

Inventor： Matthew Lucien Evans ,  Jason Parker ,  Gareth Rhys Stockwell ,  Martin Weidmann

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/46 ,  G06F12/14

Abstract: Processing circuitry (8) processes software processes at one of a plurality of exception levels and in one of a plurality of realms, each realm corresponding to a portion of at least one software process and being associated with a boundary exception level indicating a most privileged exception level at which the realm can be processed by the processing circuitry (8). In response to a realm exiting exception condition during processing of a given realm, where the exception condition is to be handled by an exception handler at a more privileged exception level than the boundary exception level of the given realm, the processing circuitry (8) performs state masking to make inaccessible, to software processes processed at a more privileged exception level than the boundary exception level, architectural state of a subset of registers selected depending on the boundary exception level of the given realm.

公开(公告)号：US11016910B2

公开(公告)日：2021-05-25

申请号：US16623999

申请日：2018-06-11

Applicant: ARM LIMITED

Inventor： Djordje Kovacevic ,  Jason Parker ,  Matthew Lucien Evans ,  Gareth Rhys Stockwell

IPC: G06F12/14 ,  G06F12/10 ,  G06Q10/10

Abstract: Apparatus for processing data uses memory access circuitry to enforce ownership rights of a plurality of memory regions within a memory, a given memory region among the plurality of memory regions having a given owning process specified from among a plurality of processes. A given owning process has exclusive rights to control access to given owned data stored within the given memory region. The memory access circuitry is responsive to a first access command from a first processing element for the given memory region to perform an access sequence comprising switching a lock flag for the given memory region to a locked state, performing an access operation specified by the access command, and switching the lock flag to an unlocked state. The memory access circuitry is responsive to a second access command from a second processing element for the given memory region while the lock flag is in said locked state to block action of the second access command.

公开(公告)号：US11009841B2

公开(公告)日：2021-05-18

申请号：US15019097

申请日：2016-02-09

Applicant: ARM LIMITED

Inventor： Håkan Persson ,  Matthew Lucien Evans

IPC: G05B19/042

Abstract: A method for initialising control data for a device comprises determining whether an identification value stored in a control storage location of the device has a first value or second value. When the identification value has the first value, space is allocated in the memory for storing the control data and an address of the allocated space in memory is written to a control data pointer storage location of the device. When the identification value has the second value, the allocation of space in memory is omitted and the control data pointer storage location comprises a preset address indicative of a location for storing the control data in local storage provided within the device.

公开(公告)号：US10102139B2

公开(公告)日：2018-10-16

申请号：US15054866

申请日：2016-02-26

Applicant: ARM LIMITED

Inventor： Matthew Lucien Evans ,  Stanislaw Czerniawski

IPC: G06F12/10 ,  G06F21/53 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/109

Abstract: A method of operation of a host data processing system which provides a virtual operating environment for one or more guest data processing systems comprises: initiating a transaction for translation of a guest system memory address to a host system physical address in response to a transaction request from a device overseen by a guest system for access to system memory at that guest system memory address; storing identification information relating to that transaction including at least data identifying device which requested the transaction; detecting a translation error condition in respect of that transaction; and handling a detected error condition by: (i) providing information indicative of the translation error condition to the guest system overseeing the device which requested the transaction; (ii) receiving a command from the guest system in respect of that transaction, the command from the guest system comprising information identifying the device which requested the transaction; and (iii) validating the received command for execution, by comparing the stored identification information for that transaction with at least the identity of the device identified by the command.

公开(公告)号：US09507728B2

公开(公告)日：2016-11-29

申请号：US14736770

申请日：2015-06-11

Applicant: ARM LIMITED

Inventor： Andrew Brookfield Swaine ,  Gareth Evans ,  Matthew Lucien Evans

IPC: G06F13/00 ,  G06F12/10 ,  G06F13/40

CPC classification number: G06F12/1009 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/1027 ,  G06F13/405 ,  G06F2212/1016 ,  G06F2212/65

Abstract: A data processing apparatus 2 includes bridge circuitry 14, 16, 18 which serves to translate memory transactions of a first type (AXI) into memory transactions of a second type (PCI Express). The bridge circuitry includes translation circuitry 18 which maps at least some of the bits of attribute data of a memory transaction of the first type to unused bits within the significant bits of an address of the second type, which are unused to represent significant bits of the address of memory transactions of the first type.

Abstract translation: 数据处理装置2包括用于将第一类型（AXI）的存储器事务转换为第二类型（PCI Express）的存储器事务的桥接电路14,16,18。 桥接电路包括转换电路18，其将第一类型的存储器事务的属性数据的位的至少一些位映射到第二类型的地址的有效位内的未使用位，其未被用于表示第二类型的有效位 第一类内存交易的地址。

公开(公告)号：US09218302B2

公开(公告)日：2015-12-22

申请号：US13926140

申请日：2013-06-25

Applicant: ARM LIMITED

Inventor： Richard Roy Grisenthwaite ,  Matthew Lucien Evans

IPC: G06F12/14 ,  G06F12/10

CPC classification number: G06F12/1475 ,  G06F12/1009 ,  G06F2212/151

Abstract: Page table data for each page within a memory address space includes a write permission flag and a dirty-bit-modifier flag. The write permission flag is initialised to a value indicating that write access is not permitted. When a write access occurs, then the dirty-bit-modifier flag indicates whether or not the action of the write permission flag may be overridden. If the action of the write permission flag may be overridden, then the write access is permitted and the write permission flag is changed to indicate that write access is thereafter permitted. A page for which the write permission flag indicates that writes are permitted is a dirty page.

Abstract translation: 存储器地址空间内的每一页的页表数据包括写允许标志和脏位修饰符标志。 写许可标志被初始化为一个值，表示不允许写访问。 当发生写入访问时，脏位修饰符标志指示是否可以覆盖写许可标志的动作。 如果可写入许可标志的动作可能被覆盖，则允许写访问，并改变写允许标志，以指示此后允许写访问。 写权限标志指示允许写入的页面是脏页。