公开(公告)号：US11841803B2

公开(公告)日：2023-12-12

申请号：US16456287

申请日：2019-06-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Skyler J. Saleh ,  Samuel Naffziger ,  Milind S. Bhagavat ,  Rahul Agarwal

IPC: G06F12/08 ,  G06F12/0897 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F12/0897 ,  G06F13/1668 ,  G06F13/4027 ,  G06F2212/1024

Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

公开(公告)号：US20230144770A1

公开(公告)日：2023-05-11

申请号：US17521578

申请日：2021-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric J. Chapman ,  Stephen Victor Kosonocky ,  Kaushik Mazumdar ,  Vydhyanathan Kalyanasundharam ,  Samuel Naffziger ,  Eric M. Scott

IPC: G06F1/30

CPC classification number: G06F1/30

Abstract: A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.

公开(公告)号：US20220189576A1

公开(公告)日：2022-06-16

申请号：US17121110

申请日：2020-12-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Ashish Jain ,  Sriram Sundaram ,  Samuel Naffziger

IPC: G11C29/50 ,  H03K3/03 ,  G11C7/22

Abstract: The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.

公开(公告)号：US11189540B2

公开(公告)日：2021-11-30

申请号：US16563138

申请日：2019-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC: H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H01L23/36 ,  H01L23/373

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.