公开(公告)号：US12170263B2

公开(公告)日：2024-12-17

申请号：US16585480

申请日：2019-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Skyler J. Saleh ,  Ruijin Wu ,  Milind S. Bhagavat ,  Rahul Agarwal

IPC: H01L23/00 ,  G06F8/41 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00 ,  H01L25/065 ,  H01L21/60

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In some embodiments, a method of manufacture includes a face-to-face process in which a first GPU chiplet and a second GPU chiplet are bonded to a temporary carrier wafer. A face surface of an active bridge chiplet is bonded to a face surface of the first and second GPU chiplets before mounting the GPU chiplets to a carrier substrate. In other embodiments, a method of manufacture includes a face-to-back process in which a face surface of an active bridge chiplet is bonded to a back surface of the first and second GPU chiplets.

公开(公告)号：US12165981B2

公开(公告)日：2024-12-10

申请号：US17556346

申请日：2021-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel H Loh ,  Raja Swaminathan ,  Rahul Agarwal ,  Brett P. Wilkerson

IPC: H01L23/538 ,  G05F1/575 ,  H01L25/065 ,  H01L27/06

Abstract: A semiconductor package includes a package substrate having a first surface and an opposing second surface, and further includes an integrated circuit (IC) die disposed at the second surface and having a third surface facing the second surface and an opposing fourth surface. The IC die has a first region comprising one or more metal layers and circuit components for one or more functions of the IC die and a second region offset from the first region in a direction parallel with the third and fourth surfaces. The semiconductor package further includes a voltage regulator disposed at the fourth surface in the second region and having an input configured to receive a supply voltage and an output configured to provide a regulated voltage, and also includes a conductive path coupling the output of the voltage regulator to a voltage input of circuitry of the IC die.

公开(公告)号：US11855061B2

公开(公告)日：2023-12-26

申请号：US17891444

申请日：2022-08-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Brett P. Wilkerson ,  Milind S. Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L23/3675 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L25/50 ,  H01L24/03 ,  H01L2224/03002 ,  H01L2224/0557 ,  H01L2224/06179 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/09179 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434

Abstract: A three-dimensional integrated circuit includes a first die structure having a first geometry. The first die structure includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The three-dimensional integrated circuit includes a second die structure having a second geometry. A stacked portion of the second die structure is aligned with the first region. The three-dimensional integrated circuit includes an additional die structure stacked with the first die structure and the second die structure. The additional die structure has the first geometry or the second geometry.

公开(公告)号：US11841803B2

公开(公告)日：2023-12-12

申请号：US16456287

申请日：2019-06-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Skyler J. Saleh ,  Samuel Naffziger ,  Milind S. Bhagavat ,  Rahul Agarwal

IPC: G06F12/08 ,  G06F12/0897 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F12/0897 ,  G06F13/1668 ,  G06F13/4027 ,  G06F2212/1024

Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

公开(公告)号：US11469183B2

公开(公告)日：2022-10-11

申请号：US17122571

申请日：2020-12-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rahul Agarwal ,  Milind S. Bhagavat

IPC: H01L23/538 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor device includes mounting an interconnect chip to a redistribution layer structure and mounting a first, second, and third semiconductor chip to the redistribution layer structure, where the second semiconductor chip is interposed between the first and the third semiconductor chips, and the interconnect chip communicatively couples the first, second and third, semiconductor chips to one another.

公开(公告)号：US11367628B2

公开(公告)日：2022-06-21

申请号：US16513450

申请日：2019-07-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Priyal Shah ,  Milind S. Bhagavat ,  Brett P. Wilkerson ,  Lei Fu ,  Rahul Agarwal

IPC: H01L21/56 ,  H01L23/31

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

公开(公告)号：US11211332B2

公开(公告)日：2021-12-28

申请号：US16778815

申请日：2020-01-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Rahul Agarwal

IPC: H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L23/52 ,  H01L25/00 ,  H01L25/18 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.

公开(公告)号：US20210296194A1

公开(公告)日：2021-09-23

申请号：US16822353

申请日：2020-03-18

Applicant: ADVANCED MICRO DEVICES, INC

Inventor： Priyal Shah ,  Rahul Agarwal ,  Milind S. Bhagavat ,  Chia-Hao Cheng

IPC: H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/304 ,  H01L23/00

Abstract: Various molded semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a routing substrate and a semiconductor chip mounted on and electrically connected to the routing substrate. The semiconductor chip has plural side surfaces. A molding layer at least partially encases the semiconductor chip. The molding layer has a tread and a riser, the riser abutting at least some of the side surfaces.

公开(公告)号：US20210098437A1

公开(公告)日：2021-04-01

申请号：US17120753

申请日：2020-12-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Rahul Agarwal

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L49/02 ,  H01L21/48

Abstract: An integrated circuit product includes a redistribution layer, an integrated circuit die disposed above the redistribution layer, a row of discrete devices disposed laterally with respect to the integrated circuit die, and encapsulant mechanically coupling the redistribution layer, integrated circuit die, and the row of discrete devices. In at least one embodiment, the row of discrete devices is a row of decoupling capacitors disposed proximate to the integrated circuit die and coupled to the integrated circuit die and a power distribution network. In at least one embodiment, a second integrated circuit die is disposed above the redistribution layer and disposed laterally with respect to the integrated circuit die and the row of discrete devices. The second integrated circuit die is mechanically coupled to the redistribution layer, integrated circuit die, and the row of discrete devices and is partially surrounded by the row of discrete devices.

公开(公告)号：US10923430B2

公开(公告)日：2021-02-16

申请号：US16458094

申请日：2019-06-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Chun-Hung Lin ,  Rahul Agarwal ,  Milind Bhagavat ,  Fei Guo

IPC: H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer and an interconnect chip at least partially encased in the first molding layer. The interconnect chip has a first side and a second side opposite the first side and a polymer layer on the first side. The polymer layer includes plural conductor traces. A redistribution layer (RDL) structure is positioned on the first molding layer and has plural conductor structures electrically connected to the plural conductor traces. The plural conductor traces provide lateral routing.