-
公开(公告)号:US12132501B2
公开(公告)日:2024-10-29
申请号:US17895227
申请日:2022-08-25
发明人: Wonjae Shin , Sung-Joon Kim , Heedong Kim , Minsu Bae , Ilwoong Seo , Mijin Lee , Seung Ju Lee , Hyan Suk Lee , Insu Choi , Kideok Han
IPC分类号: H03M13/19 , G06F11/10 , G11C5/04 , G11C8/08 , G11C11/408 , G11C11/4096 , G11C29/52 , H03M13/00
CPC分类号: H03M13/19 , G06F11/10 , G06F11/1012 , G06F11/1044 , G06F11/1048 , G11C8/08 , G11C11/4085 , G11C11/4096 , G11C29/52 , H03M13/611 , G11C5/04
摘要: A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.
-
公开(公告)号:US12132328B2
公开(公告)日:2024-10-29
申请号:US17583773
申请日:2022-01-25
发明人: Yusu Kim , Dohyeon Kim , Seho Park , Byunghwa Park
摘要: An electronic device to which a wireless charging system is applied is provided. The electronic device includes a battery, a charging circuit, and a circuit board configured to be electrically connected to the charging circuit and include a first portion and a second portion disposed adjacent to the first portion, wherein a first coil, a second coil, and a resonance coil are disposed in the first portion of the circuit board, the first coil being disposed outside the second coil, and the resonance coil being disposed inside the second coil, and wherein a third coil and a resonance capacitor are disposed in the second portion of the circuit board, the resonance capacitor being disposed inside the third coil, and the resonance coil and the resonance capacitor being electrically connected to each other to generate a designated resonance.
-
公开(公告)号:US12132119B2
公开(公告)日:2024-10-29
申请号:US17489181
申请日:2021-09-29
发明人: Kihwan Kim , Sunguk Jang , Sujin Jung , Youngdae Cho
IPC分类号: H01L29/786 , H01L21/02 , H01L29/06 , H01L29/161 , H01L29/167 , H01L29/417 , H01L29/423 , H01L29/66
CPC分类号: H01L29/78696 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0259 , H01L29/0665 , H01L29/167 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/78618
摘要: A semiconductor device includes an active region extending in a first direction on a substrate, a plurality of channel layers vertically spaced apart from each other on the active region and including a semiconductor material, a gate structure extending in a second direction on the substrate, and a source/drain region disposed on the active region on at least one side of the gate structure. The gate structure intersects the active region and the plurality of channel layers, and surrounds the plurality of channel layers. The source/drain region contacts the plurality of channel layers and includes first impurities. In at least a portion of the plurality of channel layers, a lower region adjacent to the active region includes the first impurities and second impurities at a first concentration, and an upper region includes the first impurities and the second impurities at a second concentration lower than the first concentration.
-
公开(公告)号:US12132109B2
公开(公告)日:2024-10-29
申请号:US17677654
申请日:2022-02-22
发明人: Hagyoul Bae , Seunggeol Nam , Jinseong Heo , Sanghyun Jo , Dukhyun Choe
IPC分类号: H01L29/06 , H01L21/66 , H01L29/51 , H01L29/66 , H01L29/78 , H01L29/423 , H01L29/786
CPC分类号: H01L29/78391 , H01L22/12 , H01L29/516 , H01L29/6684 , H01L29/0665 , H01L29/42392 , H01L29/7851 , H01L29/78696
摘要: Provided are a ferroelectric semiconductor device and a method of extracting a defect density of the same. A ferroelectric electronic device includes a first layer, an insulating layer including a ferroelectric layer and a first interface that is adjacent to the first layer, and an upper electrode over the insulating layer, wherein the insulating layer has a bulk defect density of 1016 cm−3eV−1 or more and an interface defect density of 1010 cm−2eV−1 or more.
-
35.
公开(公告)号:US12132044B2
公开(公告)日:2024-10-29
申请号:US16734786
申请日:2020-01-06
发明人: Sung Min Kim , Dae Won Ha
IPC分类号: H01L27/06 , H01L21/768 , H01L21/822 , H01L23/528 , H01L27/088 , H01L27/146 , H01L29/417 , H01L29/78
CPC分类号: H01L27/0688 , H01L21/76898 , H01L21/8221 , H01L23/5283 , H01L27/088 , H01L27/14636 , H01L29/4175 , H01L29/78391 , H01L29/7843 , H01L2225/06541
摘要: A semiconductor device including: a lower semiconductor substrate; an upper semiconductor substrate overlapping the lower semiconductor substrate, the upper semiconductor substrate including a first surface and a second surface opposite to the first surface; an upper gate structure on the first surface of the upper semiconductor substrate; a first interlayer insulation film which covers the upper gate structure, wherein the first interlayer insulation film is between the lower semiconductor substrate and the upper semiconductor substrate; and an upper contact connected to the lower semiconductor substrate, wherein the upper contact is on a side surface of the upper gate structure, wherein the upper contact includes a first portion penetrating the upper semiconductor substrate, and a second portion having a side surface adjacent to the side surface of the upper gate structure, and a width of the first portion decreases toward the second surface.
-
公开(公告)号:US12132037B2
公开(公告)日:2024-10-29
申请号:US17672090
申请日:2022-02-15
发明人: Jongsu Oh , Sangyoung Park , Hoseop Lee , Tetsuya Shigeta
IPC分类号: H01L25/16 , G09G3/32 , G09G3/3233 , H01L25/075 , H01L33/62
CPC分类号: H01L25/167 , G09G3/32 , G09G3/3233 , H01L25/162 , G09G2300/026 , G09G2300/0421 , G09G2300/0452 , G09G2300/0804 , G09G2310/08 , G09G2320/028 , G09G2330/12 , H01L25/0753 , H01L33/62
摘要: A display apparatus is provided having a plurality of pixels, which are arranged in M columns and N rows and arranged with a constant row space therebetween. The display apparatus includes a plurality of display modules and a housing configured to support the plurality of display modules. Each of the plurality of display modules includes a plurality of pixel packages each including some pixels of the plurality of pixels, and a plurality of micro pixel controllers each controlling the pixels included in each of the plurality of pixel packages. Each of the micro pixel controllers is disposed in the row space between the plurality of pixels to be long in a horizontal direction that is a row direction.
-
公开(公告)号:US12131999B2
公开(公告)日:2024-10-29
申请号:US18512527
申请日:2023-11-17
发明人: Jungho Do , Sanghoon Baek
IPC分类号: H01L23/528 , H01L27/02 , H01L27/092 , H01L29/423 , H01L29/786
CPC分类号: H01L23/5286 , H01L27/0207 , H01L27/092 , H01L29/42392 , H01L29/78696
摘要: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.
-
38.
公开(公告)号:US12131996B2
公开(公告)日:2024-10-29
申请号:US17739717
申请日:2022-05-09
发明人: Saehan Park , Seungyoung Lee , Inchan Hwang
IPC分类号: H01L23/528 , H01L21/78 , H01L21/822 , H01L21/8238 , H01L27/092
CPC分类号: H01L23/5286 , H01L21/7806 , H01L21/8221 , H01L21/823871 , H01L27/0922
摘要: A semiconductor device including a wafer, a first semiconductor device and a second semiconductor device on a front side of the wafer, power rails on a back side of the wafer, a backside power distribution network (PDN) grid on the back side of the wafer, and front-side signal routing lines above the first and second semiconductor devices on the front side of the wafer. The second semiconductor device is stacked on the first semiconductor device, the backside PDN grid is coupled to the power rails, and the power rails are coupled to the first and second semiconductor devices.
-
公开(公告)号:US12131995B2
公开(公告)日:2024-10-29
申请号:US18370913
申请日:2023-09-21
发明人: Seungyoon Kim , Jeongyong Sung , Sanghun Chun , Jihwan Kim , Sunghee Chung , Jeehoon Han
IPC分类号: H10B43/27 , H01L23/528 , H01L29/423
CPC分类号: H01L23/5283 , H01L29/42356 , H10B43/27
摘要: A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.
-
公开(公告)号:US12131789B2
公开(公告)日:2024-10-29
申请号:US17847545
申请日:2022-06-23
发明人: Junho Kim , Jinyoung Kim , Sehwan Park , Seoyoung Lee , Jisang Lee , Joonsuc Jang
CPC分类号: G11C16/3459 , G11C16/08 , G11C16/102 , G11C16/26 , G11C16/3404
摘要: Aggressor memory cells connected to one or more aggressor wordlines are grouped into aggressor cell groups by performing a read operation with respect to the aggressor wordlines based on one or more grouping read voltages, where the aggressor wordlines are adjacent to a selected wordline corresponding to a read address among wordlines of a memory block. Selected memory cells connected to the selected wordline are grouped into a selected cell groups respectively corresponding to the aggressor cell groups. Group read conditions respectively corresponding to the selected cell groups are determined and group read operations are performed with respect to the plurality of selected cell groups based on the group read conditions. The read errors are reduced by grouping the selected memory cells into the selected cell groups according to the change of operation environments.
-
-
-
-
-
-
-
-
-