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公开(公告)号：US07978246B2
公开(公告)日：2011-07-12
申请号：US12075516
申请日：2008-03-11
Applicant: Robert Osann, Jr. , Mary M. Fasching
Inventor： Robert Osann, Jr. , Mary M. Fasching
CPC classification number: A47F11/04 , A47F10/00 , A47F2007/195 , H04N5/64 , H04N7/181
Abstract: An Electronic Mirror is described that can capture and display, using a digital/video camera or cameras, the image of a subject as they look when viewing themselves in a mirror. The captured image is displayed on a video monitor or TV set. A widescreen flat panel monitor is utilized, having the ability to physically rotate 90°. In portrait mode the monitor functions as an Electronic Mirror, and in landscape mode is capable of functioning as a conventional TV set or video monitor. Rotation is either manual or motorized. Captured images of a subject may be split such that a portion reflecting one type of outfit may be combined with a portion reflecting a different outfit, thus electronically creating a combination of clothing that may never have been actually worn. Video capture may also be supported enabling a subject to capture and display a 360 degree view as they turn around.
Abstract translation: 描述了一种电子镜，可以使用数字/摄像机或摄像机捕获和显示当在镜子中观看自己时的主体的图像。 拍摄的图像显示在视频监视器或电视机上。 使用宽屏平板显示器，具有物理旋转90°的能力。 在纵向模式下，显示器用作电子镜像，并且在横向模式下能够用作传统的电视机或视频监视器。 旋转是手动或机动的。 拍摄对象的拍摄图像可以被分割，使得反映一种类型的装备的部分可以与反映不同衣服的部分组合，从而电子地创建可能永远不会被实际佩戴的衣服的组合。 还可以支持视频捕获，使主体能够捕获并显示360度视图，因为它们会转动。
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公开(公告)号：USRE41548E1
公开(公告)日：2010-08-17
申请号：US12191947
申请日：2008-08-14
Applicant: Robert Osann, Jr.
Inventor： Robert Osann, Jr.
CPC classification number: G06F17/5054
Abstract: An Application-Specific Field Programmable Gate Array (FPGA) device or fabric is described for use in applications requiring fast reconfigurability of devices in the field, enabling multiple personalities for re-using silicon resources (like arrays of large multipliers in DSP applications) from moment-to-moment for implementing different hardware algorithms. In a general purpose FPGA device or fabric, this fast reconfigurability is normally implemented by special reconfiguration support circuitry and/or additional configuration memory. Unfortunately, this flexibility requires a large amount of programmable routing resource and silicon area—limiting the viability in volume production applications. This invention describes how multi-program FPGA functionalities may be migrated to smaller die by constructing hybrid FPGA/ASIC implementations that retain the multi-program capability. Also described is a multi-program FPGA fabric architecture that uses a hybrid FPGA/ASIC interconnect structure, resulting in a much smaller silicon area when customized for a particular user application.
Abstract translation: 描述了应用专用现场可编程门阵列（FPGA）设备或架构，用于需要现场设备快速可重新配置的应用中，从而使多个人员能够从时刻重新使用硅资源（如DSP应用中的大乘法器阵列） 实现不同的硬件算法。 在通用FPGA设备或结构中，这种快速可重构性通常由特殊的重配置支持电路和/或附加配置存储器来实现。 不幸的是，这种灵活性需要大量的可编程路由资源和硅片区域来限制批量生产应用中的可行性。 本发明描述了如何通过构建保持多节目能力的混合FPGA / ASIC实现来将多程序FPGA功能迁移到较小的芯片。 还描述了使用混合FPGA / ASIC互连结构的多程序FPGA架构架构，当为特定用户应用定制时，导致小得多的硅面积。
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33.发明授权公开(公告)号：US07043713B2
公开(公告)日：2006-05-09
申请号：US10640171
申请日：2003-08-12
Applicant: Robert Osann, Jr. , Shafy Eltoukhy , Shridhar Mukund , Lyle Smith
Inventor： Robert Osann, Jr. , Shafy Eltoukhy , Shridhar Mukund , Lyle Smith
IPC: G06F17/50
CPC classification number: H03K19/17708 , H01L27/118
Abstract: In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.
Abstract translation: 根据本发明，公开了一种用于定制一次性可配置集成电路以包括多时间可配置结构的方法。 这种方法包括，在一个实施例中，从用户接收电路功能的描述以在一次性可配置设备中实现，其中功能包括由用户指定为可重新配置的部分。 然后，根据本发明的实施例的方法对具有足够容量以容纳指定功能的可重构结构进行建模。 可选地，本发明的一些实施例增加了比实现指定功能所需的容量更多的容量以允许将来的重新编程。 该方法然后将可重构结构嵌入在一次性可配置设备中。 在某些实施例中，一次性可配置设备可以是掩模编程的MBA，门阵列或标准单元，而可重构结构是PLA或修改的PLA。
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公开(公告)号：US06613611B1
公开(公告)日：2003-09-02
申请号：US09747129
申请日：2000-12-22
Applicant: Dana How , Robert Osann, Jr. , Eric Dellinger
Inventor： Dana How , Robert Osann, Jr. , Eric Dellinger
IPC: H01L2182
CPC classification number: H01L27/118
Abstract: A customizable ASIC routing architecture is provided. The architecture utilizes the uppermost metal layers of an ASIC composed of an array of function blocks for routing among function blocks while lower layers are used for local interconnections within the function blocks. The second-to-uppermost metal layer is fixed and generally includes a plurality of parallel segmented conductors extending in a first direction. The uppermost metal layer is customizable in a predesignated manner. Metal in the uppermost metal layer is selectively placed in tracks, which are substantially perpendicular to the segmented conductors in the layer below. Vias are provided between the two uppermost layers. One embodiment of the invention permits one-mask customization of an ASIC. Other embodiments allow a determination to be made of the ideal number of custom mask steps, taking into consideration performance, cost, time, and routability.
Abstract translation: 提供可定制的ASIC路由架构。 该架构使用由功能块阵列组成的ASIC的最上层金属层，用于在功能块之间路由，而较低层用于功能块内的本地互连。 第二至第三金属层是固定的，并且通常包括沿第一方向延伸的多个平行的分段导体。 最上层的金属层可以预先指定的方式定制。 最上层金属层中的金属被选择性地放置在跟下面的层中基本上垂直于分段导体的轨道中。 在两个最上层之间提供通孔。 本发明的一个实施例允许ASIC的单掩模定制。 考虑到性能，成本，时间和可路由性，其他实施例允许确定理想数量的定制掩模步骤。
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公开(公告)号：US06498361B1
公开(公告)日：2002-12-24
申请号：US09140087
申请日：1998-08-26
Applicant: Robert Osann, Jr.
Inventor： Robert Osann, Jr.
IPC: H01L3300
CPC classification number: G11C29/006 , G06F21/76 , G11C16/20 , G11C2029/4402 , H01L27/118
Abstract: On a wafer that includes multiple distinct designs in each die region, a memory is included in each die region. The memory stores information specific to the design implemented in the same die region. Such stored information may include a circuit design identifier or a proprietary technology identifier. Such identifiers minimize IC confusion and aid in tracking usage of proprietary technology.
Abstract translation: 在每个管芯区域中包括多个不同设计的晶片上，在每个管芯区域中包括存储器。 存储器存储在同一管芯区域中实现的设计特有的信息。 这种存储的信息可以包括电路设计标识符或专有技术标识符。 这样的标识符可以最大限度地减少IC混淆，并帮助跟踪专有技术的使用。
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Patent Agency Ranking
公开(公告)号：US5640308A
公开(公告)日：1997-06-17
申请号：US560154
申请日：1995-11-17
Applicant: Robert Osann, Jr. , George A. Shaw, Jr. , Amr M. Mohsen
Inventor： Robert Osann, Jr. , George A. Shaw, Jr. , Amr M. Mohsen
IPC: H01L23/538 , H05K1/00 , H05K1/11 , H05K7/02 , H01L29/00
CPC classification number: H01L23/5382 , H05K1/0289 , H01L2224/49171 , H01L2924/10253 , H05K1/112 , H05K2201/09945 , H05K2201/10689 , H05K2203/175
Abstract: The invention uses a programmable interconnect substrate having a plurality of conductive and interconnectable vias located on one or both surfaces thereof. A customized pattern of bonding pads is then formed over the one or both surfaces of the substrate which correspond to the terminal footprints of specific surface mounted packages intended to be mounted on the substrate. A generalized pattern of bonding pads may also be formed on the surfaces of the substrate for electrically connecting terminals of bare dice thereto by means of thin wire. All bonding pads are electrically connected to one or more vias by direct electrical contact or by a conductive trace extending from the bonding pad to a nearby via.
Abstract translation: 本发明使用具有位于其一个或两个表面上的多个导电和互连通孔的可编程互连基板。 然后在衬底的一个或两个表面上形成定制的接合焊盘图案，其对应于期望安装在衬底上的特定表面安装封装的端子脚印。 也可以在基板的表面上形成接合焊盘的一般化图案，用于通过细线电连接裸裸片的端子。 所有接合焊盘通过直接电接触或通过从接合焊盘延伸到附近的通孔的导电迹线电连接到一个或多个通孔。
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公开(公告)号：US5506850A
公开(公告)日：1996-04-09
申请号：US337132
申请日：1994-11-10
Applicant: Robert Osann, Jr.
Inventor： Robert Osann, Jr.
IPC: G01R31/3177 , G06F11/25 , H04B17/00
CPC classification number: G01R31/3177 , G06F11/25
Abstract: The invention provides a multi-stage architecture where the first stage is extremely wide and fast, but has a shallow depth which greatly reduces cost. A second stage provides a more conventional variable width/depth memory. Between the two stages is a programmable cross point switch matrix which determines which channels, of the many channels from the first stage, is to be connected as inputs to the second stage. Trigger comparisons may be performed in either or both stages.
Abstract translation: 本发明提供了一种多阶段结构，其中第一阶段非常宽且快，但是具有浅的深度，这大大降低了成本。 第二级提供更传统的可变宽/深度存储器。 在两个阶段之间是可编程交叉点开关矩阵，其确定来自第一级的许多通道中的哪些通道将作为输入连接到第二级。 触发器比较可以在两个或两个阶段中执行。
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公开(公告)号：US20230184502A1
公开(公告)日：2023-06-15
申请号：US17739679
申请日：2022-05-09
Applicant: Robert Osann, JR.
Inventor： Robert Osann, JR.
Abstract: A multi-mode and/or multi-ammunition type weapon is described, whereupon being removed from a stored position is always initially in a default mode that fires one form of ammunition type, and can be quickly placed by a user into a different mode that fires a second, and different, form of ammunition type. When returned to the stored position, an integral ammunition type selector is automatically placed into an initial position enabling the weapon to fire one of the multiple ammunition types as selected by an integral ammunition sequence selector. The ammunition sequence selector enables selection of either the first or second form of ammunition type as the default ammunition type when the weapon is placed into the stored position. A shot sequence recorder is optionally included for recording sequences of ammunition types fired, providing an un-alterable record of firing events.
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公开(公告)号：US20210156186A1
公开(公告)日：2021-05-27
申请号：US17106047
申请日：2020-11-27
Applicant: Robert Osann, JR.
Inventor： Robert Osann, JR.
IPC: E05F15/73 , E05F17/00 , E05F15/608 , E05G5/00 , E05D15/58 , E05F15/79 , E05F15/627 , E05F15/646 , E05G5/02 , E05F15/60
Abstract: Electro-mechanical and electronically controlled access devices are described for automatically controlling passage between two areas, and where a plurality of such access control devices may be ganged or clustered to provided additional throughput and directional control, including stacking a plurality of access control devices side by side within a cluster. Each access control device contains multiple rotatable and moveable door panels. The door panels are controlled by various drive mechanisms to enable passage through the device, while ensuring by the use of sensors that door panels avoid touching subjects as they traverse the device. The direction of flow through a device according to these embodiments is electronically controlled and may be changed from time to time. At any instant in time while being traversed, the flow through each device is unidirectional. Multiple devices within a cluster can be directionally controlled according to traffic, demand, time of day, or other factors.
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40.发明申请公开(公告)号：US20210089601A1
公开(公告)日：2021-03-25
申请号：US17114305
申请日：2020-12-07
Applicant: Robert Osann, JR.
Inventor： Robert Osann, JR.
IPC: G06F16/9535 , G06F16/248 , G06F16/957 , G06F16/9038 , G06F16/338
Abstract: Internet searches sometimes provide search results referencing webpages that do not contain all search term elements submitted by a user. The user may then click on such Internet search results where referenced webpages, and/or their descendants, do not contain important search term elements. Also, advertisements are sometimes placed on search results webpages that relate to the user's search term elements, even though some of those search terms are missing in referenced and/or descendant webpages. The present invention is directed to: annotating Internet search results to indicate missing search term elements on referenced and descendant webpages; optionally filtering out search results referencing webpages with missing terms; and showing advertisements related to search term elements. When shown, annotations warn the user to avoid clicking on an Internet search result where the user's search term elements are not present on referenced and/or descendant webpages, thereby preventing wasted time and speeding the search process.
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