公开(公告)号：US20040168044A1

公开(公告)日：2004-08-26

申请号：US10626479

申请日：2003-07-23

Applicant: QuickSilver Technology, Inc.

Inventor： Amit Ramchandran

IPC: G06F009/00

CPC classification number: G06F13/287 ,  G06F9/30014 ,  G06F9/3012 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3867 ,  G06F9/3885 ,  G06F13/16

Abstract: Input pipeline registers are provided at inputs to functional units and data paths in a adaptive computing machine. Input pipeline registers are used to hold last-accessed values and to immediately place commonly needed constant values, such as a zero or one, onto inputs and data lines. This approach can reduce the time to obtain data values and conserve power by avoiding slower and more complex memory or storage accesses. Another embodiment of the invention allows data values to be obtained earlier during pipelined execution of instructions. For example, in a three stage fetch-decode-execute type of reduced instruction set computer (RISC), a data value can be ready from a prior instruction at the decode or execute stage of a subsequent instruction.

Abstract translation: 在自适应计算机中的功能单元和数据路径的输入端提供输入流水线寄存器。 输入流水线寄存器用于保存最后访问的值，并将通常需要的常量值（如零或一个）放在输入和数据线上。 这种方法可以通过避免更慢和更复杂的内存或存储访问来减少获取数据值并节省功耗的时间。 本发明的另一实施例允许在流水线执行指令期间更早地获得数据值。 例如，在三阶段获取解码执行类型的精简指令集计算机（RISC）中，可以在随后指令的解码或执行阶段的先前指令准备数据值。

公开(公告)号：US20040153617A1

公开(公告)日：2004-08-05

申请号：US10356671

申请日：2003-01-31

Applicant: QuickSilver Technology, Inc.

Inventor： Frank Motta

IPC: G06F012/00 ,  G06F012/14 ,  G06F012/16 ,  G06F013/00 ,  G06F013/28

CPC classification number: G06F9/30043 ,  G06F9/3004 ,  G06F9/3824 ,  G06F11/349 ,  G06F12/023

Abstract: A system uses specialized software instructions for efficient management of freelists. In a preferred embodiment, special load and store instructions are provided. The load instruction is mapped to a register or memory location. When the load instruction is performed, hardware uses a bit-map free slot map to return an index of a free slot. Similarly, the store instruction is used to release, or free, a slot. The store instruction allows software to specify an index of a slot to be freed.

Abstract translation: 系统使用专门的软件指令来有效地管理自由职业者。 在优选实施例中，提供特殊的加载和存储指令。 加载指令映射到寄存器或存储器位置。 当执行加载指令时，硬件使用无位图自由的时隙映射来返回空闲时隙的索引。 类似地，存储指令用于释放或释放插槽。 存储指令允许软件指定要释放的插槽的索引。

公开(公告)号：US20040093589A1

公开(公告)日：2004-05-13

申请号：US10289640

申请日：2002-11-07

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master

IPC: G06F009/45

CPC classification number: G06F17/5022

Abstract: The present invention is a method, system, software and data structure for profiling programs, other code, and adaptive computing integrated circuit architectures, using a plurality of data parameters such as data type, input and output data size, data source and destination locations, data pipeline length, locality of reference, distance of data movement, speed of data movement, data access frequency, number of data load/stores, memory usage, and data persistence. The profiler of the invention accepts a data set as input, and profiles a plurality of functions by measuring a plurality of data parameters for each function, during operation of the plurality of functions with the input data set, to form a plurality of measured data parameters. From the plurality of measured data parameters, the profiler generates a plurality of data parameter comparative results corresponding to the plurality of functions and the input data set. Based upon the measured data parameters, portions of the profiled code are selected for embodiment as computational elements in an adaptive computing IC architecture.

Abstract translation: 本发明是使用诸如数据类型，输入和输出数据大小，数据源和目的地位置等多种数据参数的分析程序，其他代码和自适应计算集成电路架构的方法，系统，软件和数据结构， 数据流水线长度，参考位置，数据移动距离，数据移动速度，数据访问频率，数据加载/存储数量，内存使用情况和数据持久性。 本发明的分析器接受数据集作为输入，并且在具有输入数据集的多个功能的操作期间，通过测量每个功能的多个数据参数来分析多个功能，以形成多个测量数据参数 。 从多个测量数据参数中，轮廓仪产生对应于多个功能和输入数据组的多个数据参数比较结果。 基于所测量的数据参数，在自适应计算IC体系结构中，为了实施例而将分布代码的部分选择为计算元件。

公开(公告)号：US20040034602A1

公开(公告)日：2004-02-19

申请号：US10223256

申请日：2002-08-16

Applicant: QuickSilver Technology, Inc.

Inventor： Owen Rubin ,  Eric Murray

IPC: G06F017/60

CPC classification number: G06F21/16 ,  G06F11/3604 ,  G06F21/125

Abstract: A method and apparatus for inserting a watermark into a compiled computer program. A location process specifies an insertion point in the compiled program and a watermark generating process inserts a watermark, based on data to be encoded, into the program at the insertion point. The location process is also utilized to specify the location of watermark data to be decoded.

Abstract translation: 一种用于将水印插入到编译的计算机程序中的方法和装置。 位置处理指定编译程序中的插入点，并且水印生成处理基于要编码的数据将水印插入到插入点处的程序中。 位置处理也用于指定要解码的水印数据的位置。

公开(公告)号：US20040025159A1

公开(公告)日：2004-02-05

申请号：US10443501

申请日：2003-05-21

Applicant: QuickSilver Technology, Inc.

Inventor： W. James Scheuermann ,  Eugene B. Hogenauer

IPC: G06F009/00

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/4881 ,  G06F9/52 ,  G06F13/28 ,  G06F15/17331

Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or nullunits,null are stored into the input buffer and an associated counter is incremented. When the counter value transitions from a negative value to a zero the high-order bit of the counter is cleared, thereby indicating the input buffer has sufficient data and is available to be processed by a task.

Abstract translation: 用于管理自适应计算系统中的操作的硬件任务管理器。 任务管理器指示输入和输出缓冲区资源何时足以允许任务执行。 该任务可能需要来自一个或多个其他（或相同）任务的任意数量的输入值。 同样，在任务可以开始执行并将结果存储在输出缓冲区之前，还必须有许多输出缓冲区可用。 硬件任务管理器维护与每个输入和输出缓冲器相关联的计数器。 对于输入缓冲器，计数器的负值表示缓冲器中没有数据，因此相应的输入缓冲器尚未就绪或可用。 因此，相关任务无法运行。 预定的字节数或“单位”被存储到输入缓冲器中，相关联的计数器递增。 当计数器值从负值转换为零时，计数器的高位被清除，从而指示输入缓冲器具有足够的数据，并可由任务处理。

公开(公告)号：US20030200538A1

公开(公告)日：2003-10-23

申请号：US10127882

申请日：2002-04-23

Applicant: QuickSilver Technology, Inc.

Inventor： W. H. Carl Ebeling ,  Eugene B. Hogenauer

IPC: G06F009/45

CPC classification number: G06F8/31

Abstract: The method, system and programming language of the present invention, provide for program constructs, such as commands, declarations, variables, and statements, which have been developed to describe computations for an adaptive computing architecture, rather than provide instructions to a sequential microprocessor or DSP architecture. The invention includes program constructs that permit a programmer to define data flow graphs in software, to provide for operations to be executed in parallel, and to reference variable states and historical values in a straightforward manner. The preferred method, system, and programming language also includes mechanisms for efficiently referencing array variables, and enables the programmer to succinctly describe the direct data flow among matrices, nodes, and other configurations of computational elements and computational units forming the adaptive computing architecture. The preferred programming language includes dataflow statements, channel objects, stream variables, state variables, unroll statements, iterators, and loop statements.

Abstract translation: 本发明的方法，系统和编程语言提供了用于描述自适应计算体系结构的计算的程序结构，诸如命令，声明，变量和语句，而不是向顺序的微处理器提供指令， DSP架构。 本发明包括程序构造，其允许程序员以软件方式定义数据流图，以提供并行执行的操作，并以简单的方式引用可变状态和历史值。 优选的方法，系统和编程语言还包括有效地引用数组变量的机制，并且使程序员能够简洁地描述形成自适应计算架构的计算元素和计算单元的矩阵，节点和其他配置之间的直接数据流。 首选的编程语言包括数据流语句，通道对象，流变量，状态变量，展开语句，迭代器和循环语句。

公开(公告)号：US20030154357A1

公开(公告)日：2003-08-14

申请号：US10384486

申请日：2003-03-07

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  Eugene Hogenauer ,  Walter James Scheuermann

IPC: G06F015/00 ,  G06F015/76

CPC classification number: G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

Abstract: The present invention provides an adaptive integrated circuit. The various embodiments include a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract translation: 本发明提供一种自适应集成电路。 各种实施例包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络实时操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法操作，非线性算法操作，有限状态机操作，存储器操作 和位级操作。

公开(公告)号：US20030135743A1

公开(公告)日：2003-07-17

申请号：US10093156

申请日：2002-03-05

Applicant: QuickSilver Technology Inc.

Inventor： Walter James Scheuermann

IPC: H04K001/00

CPC classification number: G06F9/3879 ,  G06F9/30029 ,  G06F9/3895 ,  G06F15/7867 ,  G06F21/72 ,  H04L9/0643 ,  H04L2209/12

Abstract: An integrated circuit for implementing the secure hash algorithm is provided. According to one aspect of the integrated circuit, the integrated circuit includes a data path and a controller controlling operation of the data path. According to another aspect of the integrated circuit, the data path is capable of handling each round of processing reiteratively. The controller further includes an address control module and a finite state machine.

公开(公告)号：US20030126450A1

公开(公告)日：2003-07-03

申请号：US10034033

申请日：2001-12-27

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  John Watson

IPC: H04L009/00

CPC classification number: G06F21/73 ,  G06F21/10 ,  G06F21/72 ,  H04L9/0866 ,  H04L2209/12 ,  H04L2209/605 ,  H04L2209/80

Abstract: The present invention includes an apparatus, method and system for generating a configuration of an adaptive circuit which is inseparable from selected content. Either the adaptive circuit or encrypted, selected content has a unique identifier. In one of the preferred method and system embodiments in which the adaptive circuit has the unique identifier, a request for the selected content is received, along with the unique identifier, such as by a network server. The selected content is then encrypted, based upon the unique identifier, to form encrypted content. Configuration information for the adaptive circuit, corresponding to the unique identifier and the encrypted content, is generated to form corresponding configuration information. A service provider, such as through a network server, transfers the encrypted content and the corresponding configuration information to the adaptive circuit having the unique identifier, which may then be configured for use of the selected content. As a consequence, the present invention creates adaptive hardware configurations which are uniquely coupled to the selected content.

Abstract translation: 本发明包括用于生成与选定内容不可分离的自适应电路的配置的装置，方法和系统。 自适应电路或加密的所选择的内容都具有唯一的标识符。 在其中自适应电路具有唯一标识符的优选方法和系统实施例之一中，接收对所选内容的请求以及诸如网络服务器的唯一标识符。 然后，基于唯一标识符对所选择的内容进行加密，以形成加密的内容。 产生对应于唯一标识符和加密内容的自适应电路的配置信息，以形成对应的配置信息。 诸如通过网络服务器的服务提供商将加密的内容和相应的配置信息传送到具有唯一标识符的自适应电路，然后可以将其配置为使用所选择的内容。 因此，本发明创建独特地耦合到所选内容的自适应硬件配置。

公开(公告)号：US20030123666A1

公开(公告)日：2003-07-03

申请号：US10295692

申请日：2002-11-14

Applicant: QuickSilver Technology, Inc.

Inventor： Sharad Sambhwani ,  Ghobad Heidari

IPC: H04K001/00

CPC classification number: H04B1/70735 ,  H04B1/70752 ,  H04B1/708 ,  H04B1/7083 ,  H04B1/7095

Abstract: A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code's X-component being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals. According to yet another aspect of the system, each of the correlators maintains a corresponding X-component segment of the master scrambling code. For every sixteen (16) chips, a new X-component segment of the master scrambling code is introduced into one of the correlators, a X-component segment of the master scrambling code is dropped from another correlator, and X-component segments of the master scrambling code are sequentially shifted or propagated through the remaining correlators; and concurrent correlations are performed by the correlators using their respective corresponding X-component segments of the master scrambling code and newly received signals.