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    Memory device and method for estimating characteristics of multi-bit programming
    31.
    发明授权
    Memory device and method for estimating characteristics of multi-bit programming 有权
    用于估计多位编程特性的存储器件和方法

    公开(公告)号：US08305818B2

    公开(公告)日：2012-11-06

    申请号：US13303353

    申请日：2011-11-23

    Applicant: Kyoung Lae Cho ,  Seung-Hwan Song ,  Yoon Dong Park ,  Jun Jin Kong ,  Jae-Hong Kim

    Inventor： Kyoung Lae Cho ,  Seung-Hwan Song ,  Yoon Dong Park ,  Jun Jin Kong ,  Jae-Hong Kim

    IPC: G11C11/34

    CPC classification number: G11C11/5628 ,  G11C16/32 ,  G11C16/349 ,  G11C29/00 ,  G11C2211/5634

    Abstract: Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell.

    Abstract translation: 提供了可以估计多位单元特性的存储器件和/或方法。 存储器设备可以包括：多位单元阵列; 监测单元，用于提取从对应于存储在多位单元阵列中的数据的多个阈值电压状态中选择的参考阈值电压状态的时间值的阈值电压变化; 以及估计单元，用于基于所提取的阈值电压变化来估计所述多个阈值电压状态的时间值的阈值电压变化。 由此，可以监视存储单元的阈值电压随时间的变化。

    Memory device and method of storing data with error correction using codewords
    32.
    发明授权
    Memory device and method of storing data with error correction using codewords 有权
    使用码字进行纠错的存储装置和存储数据的方法

    公开(公告)号：US08301978B2

    公开(公告)日：2012-10-30

    申请号：US12453814

    申请日：2009-05-22

    Applicant: Kwang Soo Seol ,  Sung II Park ,  Kyoung Lae Cho ,  In Sung Joe

    Inventor： Kwang Soo Seol ,  Sung II Park ,  Kyoung Lae Cho ,  In Sung Joe

    IPC: G11C29/00

    CPC classification number: H03M13/611 ,  G06F11/1072 ,  G11C7/1006 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/00 ,  H03M13/13 ,  H03M13/15 ,  H03M13/27 ,  H03M13/2732 ,  H03M13/2906 ,  H03M13/3707 ,  H03M13/3715 ,  H03M13/47

    Abstract: Memory devices and/or methods of storing memory data bits are provided. A memory device includes a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it is possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability.

    Abstract translation: 提供了存储器件和/或存储存储器数据位的方法。 存储器件包括包括多个MLC的多电平单元（MLC）阵列，纠错单元，被配置为编码要记录在MLC中的数据，其中编码数据被转换以将编码数据转换为码字， 错误模式分析单元，被配置为分析与包括在码字中的错误模式相对应的码字中包含的第一数据模式;以及数据转换单元，被配置为将分析的第一数据模式转换为第二数据模式。 根据上述存储器件和/或方法，可以有效地减少在数据存储较长时间段时发生的数据错误，从而提高可靠性。

    MEMORY SYSTEM WITH INTERLEAVED ADDRESSING METHOD
    33.
    发明申请
    MEMORY SYSTEM WITH INTERLEAVED ADDRESSING METHOD 审中-公开
    具有异步寻址方法的记忆系统

    公开(公告)号：US20120246395A1

    公开(公告)日：2012-09-27

    申请号：US13426259

    申请日：2012-03-21

    Applicant: Kyoung Lae Cho ,  Hong Rak Son ,  Eun Chu Oh

    Inventor： Kyoung Lae Cho ,  Hong Rak Son ,  Eun Chu Oh

    IPC: G06F12/00

    CPC classification number: G06F12/0246 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0793 ,  G06F12/0638

    Abstract: Disclosed is a memory system which includes a nonvolatile memory device including a memory cell array having a plurality of word lines including a first set of word lines storing first data having a high bit error rate, and a second set of word lines storing second data having low bit error rate less than the high bit error rate, and a memory controller that during a program operation maps logical addresses for a portion of the first data and a portion of the second data onto a selected word line selected from the plurality of word lines.

    Abstract translation: 公开了一种包括非易失性存储器件的存储器系统，该非易失性存储器件包括具有多个字线的存储单元阵列，该多个字线包括存储具有高误码率的第一数据的第一组字线和存储具有第二数据的第二数据的第二组， 低位错误率低于高位误码率;以及存储器控制器，其在编程操作期间将用于所述第一数据的一部分和所述第二数据的一部分的逻辑地址映射到从所述多个字线中选择的所选字线上 。

    MEMORY DEVICE AND METHOD FOR ESTIMATING CHARACTERISTICS OF MULTI-BIT PROGRAMMING
    34.
    发明申请
    MEMORY DEVICE AND METHOD FOR ESTIMATING CHARACTERISTICS OF MULTI-BIT PROGRAMMING 有权
    用于估计多位编程特性的存储器件和方法

    公开(公告)号：US20120069654A1

    公开(公告)日：2012-03-22

    申请号：US13303353

    申请日：2011-11-23

    Applicant: Kyoung Lae CHO ,  Seung-Hwan Song ,  Yoong Dong Park ,  Jun Jin Kong ,  Jae Hong Kim

    Inventor： Kyoung Lae CHO ,  Seung-Hwan Song ,  Yoong Dong Park ,  Jun Jin Kong ,  Jae Hong Kim

    IPC: G11C16/04

    CPC classification number: G11C11/5628 ,  G11C16/32 ,  G11C16/349 ,  G11C29/00 ,  G11C2211/5634

    Abstract: Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell.

    Abstract translation: 提供了可以估计多位单元特性的存储器件和/或方法。 存储器设备可以包括：多位单元阵列; 监测单元，用于提取从对应于存储在多位单元阵列中的数据的多个阈值电压状态中选择的参考阈值电压状态的时间值的阈值电压变化; 以及估计单元，用于基于所提取的阈值电压变化来估计所述多个阈值电压状态的时间值的阈值电压变化。 由此，可以监视存储单元的阈值电压随时间的变化。

    Non-volatile memory device including block state confirmation cell and method of operating the same
    35.
    发明申请
    Non-volatile memory device including block state confirmation cell and method of operating the same 审中-公开
    包括块状态确认单元的非易失性存储器件及其操作方法

    公开(公告)号：US20120026790A1

    公开(公告)日：2012-02-02

    申请号：US13137668

    申请日：2011-09-01

    Applicant: Ju-hee Park ,  Jae-woong Hyun ,  Kyoung-lae Cho ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kee-won Kwon

    Inventor： Ju-hee Park ,  Jae-woong Hyun ,  Kyoung-lae Cho ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kee-won Kwon

    IPC: G11C16/10 ,  G11C16/06 ,  G11C16/04

    CPC classification number: G11C11/5642 ,  G11C2211/5641 ,  G11C2211/5646

    Abstract: Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell.

    Abstract translation: 提供了具有块状态确认单元的半导体器件，其可以存储指示写入多个存储器单元的数据位数的信息，基于写入的数据位的数量读取存储器数据的方法和/或存储器 存储指示写入数据位数的信息的编程方法。 半导体器件可以包括一个或多个存储器块和控制器。 每个存储器块可以包括存储数据的多个存储单元，以及存储指示写入存储单元的数据位数的信息的块状态确认单元。 控制器可以基于在块状态确认单元中的信息中指示的数据位数来从存储器块读取数据位。

    NON-VOLATILE MEMORY DEVICE, OPERATION METHOD THEREOF, AND DEVICES HAVING THE NON-VOLATILE MEMORY DEVICE
    39.
    发明申请
    NON-VOLATILE MEMORY DEVICE, OPERATION METHOD THEREOF, AND DEVICES HAVING THE NON-VOLATILE MEMORY DEVICE 有权
    非易失性存储器件，其操作方法和具有非易失性存储器件的器件

    公开(公告)号：US20110249495A1

    公开(公告)日：2011-10-13

    申请号：US13071727

    申请日：2011-03-25

    Applicant: Kyoung Lae Cho ,  Hyuck-Sun Kwon ,  Jun Jin Kong

    Inventor： Kyoung Lae Cho ,  Hyuck-Sun Kwon ,  Jun Jin Kong

    IPC: G11C16/04

    CPC classification number: G11C11/5628 ,  G11C16/3454

    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a memory cell array including a plurality of multi-level cells each storing data corresponding to one of a plurality of states of a first group of states, and a control circuit. The control circuit configured to program data corresponding to one of the plurality of states in a first multi-level cell according to a first verify voltage level of a first group of verify voltage levels, and to control the first multi-level cell to be re-programmed to one of a plurality of states of a second group of states according to a first verify voltage level of a second group of verify voltage levels. Each voltage level of the second group of verify voltage levels has a higher level than the verify voltage levels of the first group of verify voltage levels. One of the plurality of states of the second group of states includes at least one of the plurality of states of the first group of states.

    Abstract translation: 提供了一种非易失性存储器件。 非易失性存储器件包括存储单元阵列，其包括多个多电平单元，每个多电平单元存储与第一组状态的多个状态中的一个对应的数据，以及控制电路。 控制电路被配置为根据第一组验证电压电平的第一验证电压电平对第一多电平单元中的多个状态中的一个状态进行编程的数据，并且控制第一多电平单元被重新 根据第二验证电压电平组的第一验证电压电平编程为第二组状态的多个状态中的一个状态。 第二组验证电压电平的每个电压电平具有比第一组验证电压电平的验证电压电平更高的电平。 第二组状态的多个状态之一包括第一组状态的多个状态中的至少一个状态。

    Memory device and method of programming thereof
    40.
    发明授权
    Memory device and method of programming thereof 有权
    存储器件及其编程方法

    公开(公告)号：US08004891B2

    公开(公告)日：2011-08-23

    申请号：US12453964

    申请日：2009-05-28

    Applicant: Yong June Kim ,  Kyoung Lae Cho ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

    Inventor： Yong June Kim ,  Kyoung Lae Cho ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

    IPC: G11C16/04

    CPC classification number: G11C11/5628 ,  G11C7/1006

    Abstract: Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.

    Abstract translation: 示例性实施例可以提供存储器设备和存储器数据编程方法。 根据示例性实施例的存储器件可编码第一数据页以产生至少一个第一码字，并对第二数据页进行编码以产生第二码字。 存储器装置可以利用连续零个数的最大值和连续零数的第二最大值中的至少一个来生成第一码字。 存储器件可以将至少一个第一代码字和至少一个第二代码字编程到多个多位单元。

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