公开(公告)号：US20080111175A1

公开(公告)日：2008-05-15

申请号：US11558974

申请日：2006-11-13

Applicant: Kangguo Cheng ,  Richard O. Henry ,  Kenneth T. Settlemyer

Inventor： Kangguo Cheng ,  Richard O. Henry ,  Kenneth T. Settlemyer

IPC: H01L27/108 ,  H01L21/8242 ,  H01L21/306

CPC classification number: H01L21/32134 ,  H01L21/30608 ,  H01L27/10841 ,  H01L27/10864

Abstract: A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the of the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.

Abstract translation: 一种形成垂直DRAM装置的方法。 下沟槽填充有用于电容器的多晶或非晶半导体。 上沟槽部分具有暴露的单晶半导体的侧壁。 该方法然后包括蚀刻单晶半导体侧壁以将上部沟槽部分加宽超过电容器的半导体填充物的暴露的上表面，以在邻近上部沟槽的上部沟槽的底部上形成单晶半导体的暴露区域 半导体填充物的暴露的上表面。 沟槽顶部绝缘层沉积在上沟槽的底部上方，半导体填充物的上表面和相邻的单晶半导体区域上方。 该方法然后包括形成垂直栅极电介质层，其中沟槽顶部绝缘层延伸到垂直栅极绝缘层下方。

公开(公告)号：US07157328B2

公开(公告)日：2007-01-02

申请号：US11047312

申请日：2005-01-31

Applicant: Helmut Horst Tews ,  Stephan Kudelka ,  Kenneth T. Settlemyer

Inventor： Helmut Horst Tews ,  Stephan Kudelka ,  Kenneth T. Settlemyer

IPC: H01L21/8242

CPC classification number: H01L21/30604 ,  H01L29/66181

Abstract: The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.

Abstract translation: 在衬底中形成的沟槽的壁的表面积增加。 阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。 通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。 去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角 沟渠墙壁的交叉点。

公开(公告)号：US07138308B2

公开(公告)日：2006-11-21

申请号：US10905070

申请日：2004-12-14

Applicant: Kangguo Cheng ,  Ramachandra Divakaruni ,  Kenneth T. Settlemyer, Jr.

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Kenneth T. Settlemyer, Jr.

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/302

CPC classification number: H01L29/6656 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A field effect transistor formed by a sacrificial gate process has a simplified process and improved yield by using a tunable resistant anti-reflective coating (TERA) as the cap layer over the sacrificial gate layer. The TERA layer serves as a tunable anti-reflection layer for photolithography patterning, a hardmask for etching the sacrificial gate, a polish stopping layer for planarization, and a blocking layer for preventing silicide formation over the sacrificial gate. The TERA is stripped by a two-step process that is highly selective to the nitride spacers, so that the spacers are not damaged in the process of stripping the sacrificial gate.

Abstract translation: 通过牺牲栅极工艺形成的场效应晶体管通过使用可调阻抗抗反射涂层（TERA）作为牺牲栅极层上的覆盖层，具有简化的工艺和提高的产量。 TERA层用作光刻图案的可调谐抗反射层，用于蚀刻牺牲栅极的硬掩模，用于平坦化的抛光停止层，以及用于防止在牺牲栅极上形成硅化物的阻挡层。 通过对氮化物间隔物具有高度选择性的两步法来剥离TERA，使得在剥离牺牲栅极的过程中间隔体不被损坏。

公开(公告)号：US07101768B2

公开(公告)日：2006-09-05

申请号：US10260053

申请日：2002-09-27

Applicant: Kenneth T. Settlemyer, Jr. ,  Porshia Shane Wrschka

Inventor： Kenneth T. Settlemyer, Jr. ,  Porshia Shane Wrschka

IPC: H01L21/20

CPC classification number: H01L27/1087 ,  H01L29/66181 ,  H01L29/945

Abstract: As disclosed herein, a method is provided, in an integrated circuit, for forming an enhanced capacitance trench capacitor. The method includes forming a trench in a semiconductor substrate and forming an isolation collar on a sidewall of the trench. The collar has at least an exposed layer of oxide and occupies only a “collar” portion of the sidewall, while a “capacitor” portion of the sidewall is free of the collar. A seeding layer is then selectively deposited on the capacitor portion of the sidewall. Then, hemispherical silicon grains are deposited on the seeding layer on the capacitor portion of the sidewall. A dielectric material is deposited, and then a conductor material, in that order, over the hemispherical silicon grains on the capacitor portion of the sidewall.

Abstract translation: 如本文所公开的，在集成电路中提供用于形成增强型电容沟槽电容器的方法。 该方法包括在半导体衬底中形成沟槽并在沟槽的侧壁上形成隔离环。 套环至少具有暴露的氧化物层，并且仅占据侧壁的“套环”部分，而侧壁的“电容器”部分没有套环。 然后在侧壁的电容器部分上选择性地沉积接种层。 然后，半球状硅晶粒沉积在侧壁的电容器部分上的接种层上。 然后依次将电介质材料沉积在侧壁的电容器部分上的半球形硅晶粒上。