公开(公告)号：US20070152281A1

公开(公告)日：2007-07-05

申请号：US11616255

申请日：2006-12-26

申请人： Jung Ho Ahn

发明人： Jung Ho Ahn

IPC分类号： H01L29/76

CPC分类号： H01L29/4238 ,  H01L29/78

摘要： A MOS transistor may include at least one of: a channel having a width W0 and a length L0; an active area with a channel between a source area and a drain area; a gate insulating layer formed over a channel; and/or a gate conductor formed over a gate insulating layer and intersecting the active area. In embodiments, a gate conductor may include at least one of: a connection pattern formed with a gate contact hole which electrically connects the gate conductor to the outside; an additional pattern connected to a connection pattern and positioned in parallel with both source and drain areas while being spaced apart from the active area at a certain distance; and a channel pattern connected to an additional pattern in the shape of a T and defining the length of a channel.

摘要翻译： MOS晶体管可以包括以下至少一个：具有宽度W 0和长度L 0的沟道; 具有在源区域和漏极区域之间的通道的有源区域; 形成在通道上的栅极绝缘层; 和/或形成在栅极绝缘层上并与有源区相交的栅极导体。 在实施例中，栅极导体可以包括以下中的至少一个：形成有栅极接触孔的连接图案，其将栅极导体电连接到外部; 连接到连接图案并且与源极和漏极区域平行定位的附加图案，同时在一定距离处与有源区域间隔开; 以及连接到T形状的附加图案并定义通道的长度的通道图案。

公开(公告)号：US08959292B1

公开(公告)日：2015-02-17

申请号：US11643026

申请日：2006-12-20

申请人： Jung Ho Ahn ,  Mattan Erez ,  William J. Dally

发明人： Jung Ho Ahn ,  Mattan Erez ,  William J. Dally

IPC分类号： G06F12/00 ,  G06F9/38 ,  G06F3/06

CPC分类号： G06F3/067 ,  G06F9/3895 ,  G06F12/0802

摘要： Atomic memory access requests are handled using a variety of systems and methods. According to one example method, a data-processing circuit having an address-request generator that issues requests to a common memory implements a method of processing the requests using a memory-access intervention circuit coupled between the generator and the common memory. The method identifies a current atomic-memory access request from a plurality of memory access requests. A data set is stored that corresponds to the current atomic-memory access request in a data storage circuit within the intervention circuit. It is determined whether the current atomic-memory access request corresponds to at least one previously-stored atomic-memory access request. In response to determining correspondence, the current request is implemented by retrieving data from the common memory. The data is modified in response to the current request and at least one other access request in the memory-access intervention circuit.

摘要翻译： 使用各种系统和方法来处理原子存储器访问请求。 根据一个示例性方法，具有向公共存储器发出请求的地址请求生成器的数据处理电路实现使用耦合在发生器和公共存储器之间的存储器访问干预电路来处理请求的方法。 该方法从多个存储器访问请求中识别当前的原子存储器访问请求。 存储对应于干预电路内的数据存储电路中的当前原子存储器访问请求的数据集。 确定当前的原子存储器访问请求是否对应于至少一个先前存储的原子存储器访问请求。 响应于确定对应关系，通过从公共存储器检索数据来实现当前请求。 响应于当前请求和存储器访问干预电路中的至少一个其他访问请求修改数据。

公开(公告)号：US08938139B2

公开(公告)日：2015-01-20

申请号：US12921768

申请日：2008-03-11

申请人： Moray McLaren ,  Jung Ho Ahn ,  Nathan L. Binkert ,  Alan L. Davis ,  Norman Paul Jouppi

发明人： Moray McLaren ,  Jung Ho Ahn ,  Nathan L. Binkert ,  Alan L. Davis ,  Norman Paul Jouppi

IPC分类号： G02B6/26 ,  G02B6/12 ,  G02F1/313 ,  H04Q11/00 ,  G02B6/293 ,  G02B6/35

CPC分类号： G02B6/12007 ,  G02B6/29338 ,  G02B6/35 ,  G02B6/3546 ,  G02B6/356 ,  G02F1/3137 ,  G02F1/3138 ,  G02F2201/17 ,  G02F2202/32 ,  G02F2203/15 ,  H04Q11/0005 ,  H04Q11/0066 ,  H04Q2011/0016 ,  H04Q2011/0035 ,  H04Q2011/0058

摘要： Embodiments of the present invention are directed to optoelectronic network switches. In one embodiment, an optoelectronic switch includes a set of roughly parallel input waveguides and a set of roughly parallel output waveguides positioned roughly perpendicular to the input waveguides. Each of the output waveguides crosses the set of input waveguides. The optoelectronic switch includes at least one switch element configured to switch one or more optical signals transmitted on one or more input waveguides onto one or more crossing output waveguides.

摘要翻译： 本发明的实施例涉及光电网络交换机。 在一个实施例中，光电开关包括一组大致平行的输入波导和大致垂直于输入波导定位的大致平行的输出波导组。 每个输出波导穿过该组输入波导。 光电开关包括至少一个开关元件，其被配置为将在一个或多个输入波导上传输的一个或多个光信号切换到一个或多个交叉输出波导上。

公开(公告)号：US08924639B2

公开(公告)日：2014-12-30

申请号：US13058048

申请日：2008-08-08

申请人： Jung Ho Ahn ,  Norman P. Jouppi ,  Robert S. Schreiber

发明人： Jung Ho Ahn ,  Norman P. Jouppi ,  Robert S. Schreiber

IPC分类号： G06F12/00 ,  G06F12/06 ,  G11C5/04 ,  G11C8/12 ,  G06F13/16

CPC分类号： G11C5/04 ,  G06F12/06 ,  G06F12/0646 ,  G06F13/1684 ,  G06F2212/1028 ,  G11C8/12 ,  Y02D10/13 ,  Y02D10/14

摘要： Various embodiments of the present invention are directed multi-core memory modules. In one embodiment, a memory module (500) includes memory chips, and a demultiplexer register (502) electronically connected to each of the memory chips and a memory controller. The memory controller groups one or more of the memory chips into at least one virtual memory device in accordance with changing performance and/or energy efficiency needs. The demultiplexer register (502) is configured to receive a command indentifying one of the virtual memory devices and send the command to the memory chips of the identified virtual memory device. In certain embodiments, the memory chips can be dynamic random access memory chips.

摘要翻译： 本发明的各种实施例是多核存储器模块。 在一个实施例中，存储器模块（500）包括存储器芯片和电连接到每个存储器芯片的解复用器寄存器（502）和存储器控制器。 存储器控制器根据改变的性能和/或能量效率需求将一个或多个存储器芯片组合成至少一个虚拟存储器设备。 解复用器寄存器（502）被配置为接收识别虚拟存储器设备中的一个并且将命令发送到所识别的虚拟存储器设备的存储器芯片的命令。 在某些实施例中，存储器芯片可以是动态随机存取存储器芯片。

公开(公告)号：US08054231B2

公开(公告)日：2011-11-08

申请号：US12419503

申请日：2009-04-07

申请人： Jung Ho Ahn ,  Yong Jin Kim ,  Dong Hwan Kim ,  Jae Ho Lee ,  Seung Hwan Kim

发明人： Jung Ho Ahn ,  Yong Jin Kim ,  Dong Hwan Kim ,  Jae Ho Lee ,  Seung Hwan Kim

IPC分类号： H01Q1/24 ,  H01Q13/10

CPC分类号： H01Q1/243 ,  H01Q13/106

摘要： A mobile terminal including a metal case and an antenna structure that can exhibit optimum radiation performance is provided. The antenna structure includes an antenna having a radiation unit for transmitting and for receiving electric waves, a Printed Circuit Board (PCB) to which the antenna is mechanically coupled at one surface thereof and having a power supply unit electrically coupled to the radiation unit, and a case constructed using a metal material within which the PCB is disposed, wherein the case has at least one slot formed in a surface thereof opposite to the surface to which the PCB is fastened and adjacent to the radiation unit.

摘要翻译： 提供一种包括金属外壳和能够呈现最佳辐射性能的天线结构的移动终端。 天线结构包括具有用于发送和接收电波的辐射单元的天线，天线在其一个表面机械耦合并具有电耦合到辐射单元的电源单元的印刷电路板（PCB），以及 使用其中布置有PCB的金属材料构造的壳体，其中所述壳体具有形成在其与所述PCB被紧固并邻近所述辐射单元的表面相对的表面中的至少一个槽。

公开(公告)号：US07638389B2

公开(公告)日：2009-12-29

申请号：US11957982

申请日：2007-12-17

申请人： Jung-Ho Ahn

发明人： Jung-Ho Ahn

IPC分类号： H01L21/8242

CPC分类号： H01L29/94 ,  H01L27/0629 ,  H01L28/40

摘要： A semiconductor device capacitor fabrication method that is capable of enabling the simultaneous use of an oxide capacitor and a PIP capacitor of a semiconductor device depending upon whether metal line terminals are used. The semiconductor device capacitor fabrication method can include forming an active region and a first gate electrode over a semiconductor substrate, partially depositing a silicon nitride layer, over which a capacitor will be formed, over the first gate electrode, forming a second gate electrode over the silicon nitride, sequentially forming a first insulation layer and a second insulation layer over the resultant structure and forming line terminals extending through the first insulating layer and the second insulating layer for a transistor and a capacitor.

摘要翻译： 一种半导体器件电容器制造方法，其能够根据金属线端子是否能够同时使用半导体器件的氧化物电容器和PIP电容器。 半导体器件电容器制造方法可以包括在半导体衬底上形成有源区和第一栅电极，在第一栅电极上部分地沉积氮化硅层，在其上形成电容器，在其上形成第二栅电极 氮化硅，在所得结构上依次形成第一绝缘层和第二绝缘层，并形成延伸穿过第一绝缘层的线端子和用于晶体管和电容器的第二绝缘层。

公开(公告)号：US07528455B2

公开(公告)日：2009-05-05

申请号：US11646727

申请日：2006-12-27

申请人： Jung Ho Ahn

发明人： Jung Ho Ahn

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/10 ,  H01L29/739 ,  H01L29/73

CPC分类号： H01L29/41758 ,  H01L29/78

摘要： Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.

摘要翻译： 公开了一种用于增强PMOS和NMOS晶体管的性能的半导体晶体管，特别是电流驱动性能，同时减小窄宽度效应。 窄宽度的MOS晶体管包括：宽度为W0且长度为L0的沟道; 一个有效区域，包括以通道为中心形成在两侧的源区和漏区; 形成在所述通道上的栅极绝缘层; 栅极导体，形成在栅极绝缘层上并与有源区相交; 宽度的第一附加有效区域大于作为添加到源区域的活动区域的信道的W0; 并且宽度的第二附加有源区域大于作为添加到漏极区域的有源区域的沟道的W0。 当具有附加有源区的晶体管的结构被施加到NMOS和PMOS晶体管时，驱动电流分别表示为107.27％和103.31％。 因此，增加了PMOS和NMOS晶体管的驱动电流。

公开(公告)号：US08812886B2

公开(公告)日：2014-08-19

申请号：US13058067

申请日：2008-08-13

申请人： Jung Ho Ahn ,  Norman P. Jouppi ,  Jacob B. Leverich ,  Robert S. Schreiber

发明人： Jung Ho Ahn ,  Norman P. Jouppi ,  Jacob B. Leverich ,  Robert S. Schreiber

IPC分类号： G06F1/32 ,  G06F12/02 ,  G06F13/16 ,  G11C5/04 ,  G11C7/20

CPC分类号： G06F12/0215 ,  G06F1/3203 ,  G06F13/1694 ,  G06F2212/1028 ,  G11C5/04 ,  G11C7/20 ,  Y02D10/13 ,  Y02D10/152

摘要： Various embodiments of the present invention are directed to methods that enable a memory controller to choose a particular operation mode for virtual memory devices of a memory module based on dynamic program behavior. In one embodiment, a method for determining an operation mode for each virtual memory device of a memory module includes selecting a metric (1001) that provides a standard by which performance and/or energy efficiency of the memory module is optimized during execution of one or more applications on a multicore processor. For each virtual memory device (1005), the method also includes collecting usage information (1006) associated with the virtual memory device over a period of time, determining an operation mode (1007) for the virtual memory device based on the metric and usage information, and entering the virtual memory device into the operation mode (1103, 1105, 1107, 1108).

摘要翻译： 本发明的各种实施例涉及使存储器控制器能够基于动态程序行为为存储器模块的虚拟存储器件选择特定操作模式的方法。 在一个实施例中，一种用于确定存储器模块的每个虚拟存储器设备的操作模式的方法包括：选择度量（1001），其提供在执行一个或多个存储器模块期间优化存储器模块的性能和/或能量效率的标准 多核处理器上的更多应用程序。 对于每个虚拟存储设备（1005），该方法还包括在一段时间内收集与虚拟存储设备相关联的使用信息（1006），基于度量和使用信息确定虚拟存储设备的操作模式（1007） ，并且进入虚拟存储设备进入操作模式（1103,1105,1107,1108）。

公开(公告)号：US20120189026A1

公开(公告)日：2012-07-26

申请号：US13259468

申请日：2009-10-08

申请人： Nathan Lorenzo Binkert ,  Jung Ho Ahn ,  Marco Florentino

发明人： Nathan Lorenzo Binkert ,  Jung Ho Ahn ,  Marco Florentino

IPC分类号： H01S3/11

CPC分类号： G02B6/29341 ,  G02F1/2257 ,  G02F2203/15

摘要： Various embodiments of the present invention relate to electronically tunable ring resonators. In one embodiment of the present invention, a resonator structure (300,1200) includes an inner resonator disposed on a surface of a substrate, and a phase-change layer (304,1204) covering the resonator. The resonance wavelength of the resonator structure can be selected by applying of a first voltage that changes the effective refractive index of the inner resonator and by applying of a second voltage that changes the effective refractive index of the phase-change layer.

摘要翻译： 本发明的各种实施例涉及电子可调谐环形谐振器。 在本发明的一个实施例中，谐振器结构（300,1200）包括设置在衬底的表面上的内谐振器和覆盖谐振器的相变层（304,1204）。 谐振器结构的谐振波长可以通过施加改变内部谐振器的有效折射率的第一电压和施加改变相变层的有效折射率的第二电压来选择。

公开(公告)号：US20110145493A1

公开(公告)日：2011-06-16

申请号：US13058188

申请日：2008-08-08

申请人： Jung Ho Ahn ,  Norman P. Jouppi ,  Jacob B. Erich

发明人： Jung Ho Ahn ,  Norman P. Jouppi ,  Jacob B. Erich

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/06 ,  G06F13/1668 ,  G11C5/04 ,  G11C8/12 ,  Y02D10/13 ,  Y02D10/14

摘要： Various embodiments of the present invention are directed a multi-core memory modules. In one embodiment, a memory module (500) includes at least one virtual memory device and a demultiplexer register (502) disposed between the at least one virtual memory device and a memory controller. The demultiplexer register receives a command identifying one of the at least one virtual memory devices from the memory controller and sends the command to the identified virtual memory device. In addition, the at least one virtual memory devices include at least one memory chip.

摘要翻译： 本发明的各种实施例涉及多核存储器模块。 在一个实施例中，存储器模块（500）包括设置在至少一个虚拟存储器设备和存储器控制器之间的至少一个虚拟存储器设备和解复用器寄存器（502）。 解复用器寄存器从存储器控制器接收识别至少一个虚拟存储器设备中的一个的命令，并将该命令发送到所识别的虚拟存储设备。 另外，至少一个虚拟存储器设备包括至少一个存储器芯片。