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    METHOD OF LINEARIZING THE TRANSFER CHARACTERISTIC BY DYNAMIC ELEMENT MATCHING
    31.
    发明申请
    METHOD OF LINEARIZING THE TRANSFER CHARACTERISTIC BY DYNAMIC ELEMENT MATCHING 审中-公开

    公开(公告)号：US20190280704A1

    公开(公告)日：2019-09-12

    申请号：US16053455

    申请日：2018-08-02

    Applicant: Analog Devices Global Unlimited Company

    Inventor： Rares BODNAR ,  Roberto S. MAURINO ,  Christopher Peter HURRELL ,  Asif AHMAD

    IPC: H03M1/06

    Abstract: A stage, suitable for use in and analog to digital converter or a digital to analog converter, comprises a plurality of slices. The slices can be operated together to form a composite output having reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance. The slices can be sub-divided to reduce scaling mismatch between the most significant bit and the least significant bit. A shuffling scheme is implemented that allows shuffling to occur between the sub-sections of the slices without needing to implement a massively complex shuffler.

    Interleaved boost converter with holdup time extension
    33.
    发明授权
    Interleaved boost converter with holdup time extension 有权

    公开(公告)号：US10367411B2

    公开(公告)日：2019-07-30

    申请号：US15849047

    申请日：2017-12-20

    Applicant: Analog Devices Global Unlimited Company

    Inventor： Francis Martin

    IPC: H02M7/04 ,  H02M1/42 ,  G05F1/70 ,  H02M1/32 ,  H02M7/219 ,  H02M3/337

    Abstract: A power factor correction device for providing tolerance to a fault condition in an input supply can include a first boost circuit, a second boost circuit, and a controller circuit. The controller circuit can interleave operation of the first boost circuit and operation of the second boost circuit such as to generate an output voltage when the input supply is received at the power factor correction device. The controller circuit can route, in response to the fault condition, a stored supply of the second boost circuit to an input of the first boost circuit. The controller circuit can control the first boost circuit to maintain the output voltage.

    CURRENT STEERING DIGITAL TO ANALOG CONVERTER
    37.
    发明申请
    CURRENT STEERING DIGITAL TO ANALOG CONVERTER 审中-公开

    公开(公告)号：US20190140656A1

    公开(公告)日：2019-05-09

    申请号：US15895661

    申请日：2018-02-13

    Applicant: Analog Devices Global Unlimited Company

    Inventor： Fergus John Downey

    IPC: H03M1/78

    Abstract: Digital to analog converter architectures are disclosed that enable the binary scaling of transistor sized to be replaced by transistors of substantially the same size. This significantly reduced the size of the Digital to Analog converter on a wafer. As the currents from the lesser bits of the converter may be very small indeed, some of the transistors are operated in a regime where the gate-source voltage applied to the transistor is below the threshold voltage for the device, the threshold voltage generally being regarded as marking the onset of significant conduction through a field effect transistor.

    Method to improve latency in an ethernet PHY device
    38.
    发明授权
    Method to improve latency in an ethernet PHY device 有权

    公开(公告)号：US10277433B1

    公开(公告)日：2019-04-30

    申请号：US15813905

    申请日：2017-11-15

    Applicant: Analog Devices Global Unlimited Company

    Inventor： Jacobo Riesco-Prieto ,  Philip Curran ,  Michael McCarthy

    IPC: H04L1/00 ,  H04L25/08 ,  H04L25/49 ,  H04L27/00

    Abstract: This disclosure relates to data communication networks. An example data communication apparatus includes physical (PHY) layer circuitry that includes transceiver circuitry, decoder circuitry, and a signal analysis unit. The transceiver circuitry receives encoded data symbols via a network link. The received encoded data symbols are encoded using trellis coded modulation (TCM). The decoder circuitry decodes the received encoded data symbols using maximum-likelihood (ML) decoding to map a received symbol sequence to an allowed symbol sequence using a trace-back depth. A trace-back depth value is a number of symbols in the received symbol sequence used by the ML decoding to identify the allowed symbol sequence from the received symbol sequence. The signal analysis unit determines one or more link statistics of the network link, and sets the trace-back depth value according to the one or more link statistics.

    Tank circuit and frequency hopping for isolators
    39.
    发明授权
    Tank circuit and frequency hopping for isolators 有权

    公开(公告)号：US10164614B2

    公开(公告)日：2018-12-25

    申请号：US15087723

    申请日：2016-03-31

    Applicant: Analog Devices Global Unlimited Company

    Inventor： Xin Yang ,  Tianting Zhao ,  Baoxing Chen

    IPC: H03B5/12 ,  H03K3/013 ,  H03B5/08

    Abstract: Embodiments of the present disclosure may provide a circuit comprising a tank circuit. The tank circuit may include an inductor having a pair of terminals, a first pair of transistors, and a first pair of capacitors. Each transistor may be coupled between a respective terminal of the inductor and a reference voltage along a source-to-drain path of the transistor. Each capacitor may be provided in a signal path between an inductor terminal coupled to a respective first transistor in the first pair and a gate of a second transistor in the first pair.

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