公开(公告)号：US20180314221A1

公开(公告)日：2018-11-01

申请号：US15958871

申请日：2018-04-20

Applicant: Analog Devices Global Unlimited Company

Inventor： Navdeep Singh Dhanjal ,  Shengbing Zhou

IPC: G05B19/045 ,  G06F1/32 ,  G06F12/0817 ,  H03K19/00

CPC classification number: G05B19/045 ,  G05B2219/23289 ,  G06F1/3296 ,  G06F12/0824 ,  H03K19/0002

Abstract: An apparatus comprises an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the sequencer circuitry is configured to: receive one or more control words from the hierarchical linked lists associated with an IC state; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state.

公开(公告)号：US10310476B2

公开(公告)日：2019-06-04

申请号：US15958871

申请日：2018-04-20

Applicant: Analog Devices Global Unlimited Company

Inventor： Navdeep Singh Dhanjal ,  Shengbing Zhou

IPC: H03K19/173 ,  G05B19/045 ,  G06F1/3296 ,  H03K19/00 ,  G06F12/0817

Abstract: An apparatus comprises an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the sequencer circuitry is configured to: receive one or more control words from the hierarchical linked lists associated with an IC state; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state.