公开(公告)号：US11289603B2

公开(公告)日：2022-03-29

申请号：US16944768

申请日：2020-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3115 ,  H01L29/66

Abstract: A semiconductor device and method of manufacture are provided which utilizes metallic seeds to help crystallize a ferroelectric layer. In an embodiment a metal layer and a ferroelectric layer are formed adjacent to each other and then the metal layer is diffused into the ferroelectric layer. Once in place, a crystallization process is performed which utilizes the material of the metal layer as seed crystals.

公开(公告)号：US11282945B2

公开(公告)日：2022-03-22

申请号：US16596059

申请日：2019-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/78

Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.

公开(公告)号：US20220059671A1

公开(公告)日：2022-02-24

申请号：US17521344

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Chih-Yu Chang ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

公开(公告)号：US20220037321A1

公开(公告)日：2022-02-03

申请号：US17157182

申请日：2021-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Chunyao Wang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

公开(公告)号：US11227956B2

公开(公告)日：2022-01-18

申请号：US16882965

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Bo-Feng Young ,  Chien Ning Yao ,  Chi On Chui

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor device includes: a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions, where the nanosheets comprise a first semiconductor material; inner spacers between the nanosheets and at opposite ends of the nanosheets, where there is an air gap between each of the inner spacers and a respective source/drain region of the source/drain regions; and a gate structure over the fin and between the source/drain regions.

公开(公告)号：US20220013364A1

公开(公告)日：2022-01-13

申请号：US16923658

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/8238

Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

公开(公告)号：US20210407807A1

公开(公告)日：2021-12-30

申请号：US17023486

申请日：2020-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Ping Wang ,  Ting-Gang Chen ,  Bo-Cyuan Lu ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/764 ,  H01L21/8234

Abstract: A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.

公开(公告)号：US20210399102A1

公开(公告)日：2021-12-23

申请号：US16909260

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AlW); and a fill material over the first work function tuning layer.

公开(公告)号：US20210376105A1

公开(公告)日：2021-12-02

申请号：US17145925

申请日：2021-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.

公开(公告)号：US20210335657A1

公开(公告)日：2021-10-28

申请号：US17025528

申请日：2020-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Cyuan Lu ,  Ting-Gang Chen ,  Sung-En Lin ,  Chunyao Wang ,  Yung-Cheng Lu ,  Chi On Chui ,  Tai-Chun Huang ,  Chieh-Ping Wang

IPC: H01L21/762 ,  H01L21/311

Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.