公开(公告)号：US08830099B1

公开(公告)日：2014-09-09

申请号：US13748177

申请日：2013-01-23

申请人： Maxim Integrated Products, Inc.

发明人： Matthew Straayer ,  Hae-Sung Lee ,  Kush Gulati

IPC分类号： H03M1/66

CPC分类号： H03M1/06 ,  H03M1/0612 ,  H03M1/164 ,  H03M1/66

摘要： Various embodiments of the invention provide for cancellation of a residue amplifier output charging current at the reference voltage source of the reference buffer thereby preventing the charging current from altering the effective reference voltage of a reference buffer. In certain embodiments, current cancellation is accomplished by subtracting a current of the same magnitude.

摘要翻译： 本发明的各种实施例提供了在参考缓冲器的参考电压源处取消残余放大器输出充电电流，从而防止充电电流改变参考缓冲器的有效参考电压。 在某些实施例中，通过减去相同幅度的电流来实现电流消除。

公开(公告)号：US08786475B2

公开(公告)日：2014-07-22

申请号：US13498513

申请日：2010-08-28

申请人： Bjornar Hernes

发明人： Bjornar Hernes

IPC分类号： H03M1/00

CPC分类号： H03M1/1245 ,  G11C27/024 ,  H03M1/1215 ,  H03M1/164 ,  H03M1/44

摘要： A circuit includes an input, two or more sampling capacitors each in a different channel, means for connecting each sampling capacitor to the input, means for discharging the sampling capacitors to a given voltage in a reset phase, and means to use the voltage across the sampling capacitor for further processing in a hold phase. The two sampling capacitors operate in anti-phase such that the reset phase and sampling phase of one channel are performed in the time period the other channel is in the hold phase.

摘要翻译： 一个电路包括一个输入端，两个或更多个采样电容器，每个在不同的通道中，每个采样电容器连接到输入端的装置，用于将采样电容器放电到复位阶段的给定电压的装置， 采样电容器用于在保持阶段进一步处理。 两个采样电容器以反相方式工作，使得一个通道的复位相位和采样相位在另一个通道处于保持阶段的时间段内执行。

公开(公告)号：US08760337B2

公开(公告)日：2014-06-24

申请号：US13748111

申请日：2013-01-23

申请人： Canon Kabushiki Kaisha

发明人： Kazuo Yamazaki

IPC分类号： H03M1/12

CPC分类号： H03M1/12 ,  H03M1/123 ,  H03M1/164 ,  H03M1/56

摘要： A solid-state image sensing device comprises a pixel which outputs a pixel signal, a first conversion unit which converts the pixel signal into a digital signal with a first bit length, and a second conversion unit which converts, into a digital signal with a second bit length, an analog signal obtained by subtracting, from the pixel signal, an analog signal corresponding to the digital signal with the first bit length. The second conversion unit comprises a current source, a first capacitance, and a switching unit for switching a supply destination of a current supplied from the current source to one of the first capacitance and a reference potential. The second conversion unit performs the conversion based on comparison between a reference voltage and the analog signal which is charged in the first capacitance and is obtained as a subtraction result.

摘要翻译： 固态图像感测装置包括输出像素信号的像素，将像素信号转换为具有第一位长度的数字信号的第一转换单元，以及将第二转换单元转换成具有第二位长度的数字信号的第二转换单元 比特长度，通过从像素信号中减去与第一比特长度相对应的数字信号的模拟信号而获得的模拟信号。 第二转换单元包括电流源，第一电容和用于将从电流源提供的电流的供给目的地切换到第一电容和参考电位之一的开关单元。 第二转换单元基于参考电压与在第一电容中充电的模拟信号之间的比较来执行转换，并作为减法结果获得。

公开(公告)号：US08760335B1

公开(公告)日：2014-06-24

申请号：US14164369

申请日：2014-01-27

申请人： IQ-Analog Corporation

发明人： Michael Kappes

IPC分类号： H03M1/12

CPC分类号： H03M1/12 ,  H03M1/005 ,  H03M1/007 ,  H03M1/0643 ,  H03M1/1215 ,  H03M1/164 ,  H03M1/44 ,  H03M3/462

摘要： A data converter module is provided with an analog interface to receive analog signals, a digital interface to transmit digital signals, and a configuration interface to accept configuration signals. The data conversion module also includes a data conversion array (DCA) with selectively engageable data conversion circuits for the conversion of analog input signals to digital output signals, where the data conversion circuits are responsive to the configuration signals. The DCA's data conversion circuits include configurable data resolution circuits and configurable data conversion speed circuits. For example, the configurable data resolution circuits may be selected from averaging, oversampling, and multi-stage pipelining circuits. The DCA configurable data speed circuit may interleave the outputs from multiple parallelly connected ADCs operating at different clock phases. In one aspect, the number of clock phases is selectable. Also provided are methods for configurable data conversion.

摘要翻译： 数据转换器模块具有模拟接口以接收模拟信号，数字接口传输数字信号，配置接口接受配置信号。 数据转换模块还包括具有选择性地可接合的数据转换电路的数据转换阵列（DCA），用于将模拟输入信号转换成数字输出信号，其中数据转换电路响应于配置信号。 DCA的数据转换电路包括可配置数据分辨率电路和可配置数据转换速度电路。 例如，可以从平均，过采样和多级流水线电路中选择可配置数据分辨率电路。 DCA可配置数据速度电路可以对来自在不同时钟阶段工作的多个并联连接的ADC的输出进行交织。 在一个方面，时钟相位的数量是可选择的。 还提供了可配置数据转换的方法。

公开(公告)号：US08717219B2

公开(公告)日：2014-05-06

申请号：US13780685

申请日：2013-02-28

申请人： Kabushiki Kaisha Toshiba

发明人： Jun Deguchi

IPC分类号： H03M1/38

CPC分类号： H03M1/002 ,  H03M1/0682 ,  H03M1/164 ,  H03M1/466

摘要： According to one embodiment, a semiconductor integrated circuit is configured to convert a difference between a first analog voltage and a second analog voltage into a digital signal. The semiconductor integrated circuit includes m (m is an integer greater than or equal to 2) first capacitors and second capacitors. Each of the m capacitors has a first electrode and a second electrode, and the first electrodes are connected to each other. Each of the m second capacitors has a third electrode and a fourth electrode, and the third electrodes are connected to each other. The semiconductor integrated circuits further includes: a comparator configured to compare a voltage of the first electrode and a voltage of the third electrode; and a logic circuit configured to generate the digital signal based on a comparison result of the comparator.

摘要翻译： 根据一个实施例，半导体集成电路被配置为将第一模拟电压和第二模拟电压之间的差转换为数字信号。 半导体集成电路包括m（m是大于或等于2的整数）第一电容器和第二电容器。 m个电容器中的每一个具有第一电极和第二电极，并且第一电极彼此连接。 每个m个第二电容器具有第三电极和第四电极，并且第三电极彼此连接。 半导体集成电路还包括：比较器，被配置为比较第一电极的电压和第三电极的电压; 以及逻辑电路，被配置为基于比较器的比较结果生成数字信号。

公开(公告)号：US08686888B2

公开(公告)日：2014-04-01

申请号：US13543386

申请日：2012-07-06

申请人： Wei-Te Chou ,  Jiangfeng Wu ,  Wenbo Liu

发明人： Wei-Te Chou ,  Jiangfeng Wu ,  Wenbo Liu

IPC分类号： H03M1/38

CPC分类号： H03F3/005 ,  H03F3/265 ,  H03F3/3001 ,  H03F3/45179 ,  H03F2203/45551 ,  H03M1/164

摘要： The present disclosure is directed to a switched capacitor amplifier that includes a switched capacitor network and a complementary push-pull amplifier. The switched capacitor amplifier of the present disclosure can provide a larger fraction of the charge provided by a power supply and flowing through the amplifier to a capacitive load at the output of the amplifier compared to switched capacitor amplifiers that use single-ended class-A amplifiers. The switched capacitor amplifier of the present disclosure can be used in a converter stage of a pipelined analog-to-digital converter (ADC) to improve the ADC's power efficiency and/or bandwidth. It can be further generalized to be used in other applications other than pipelined ADCs.

摘要翻译： 本公开涉及一种包括开关电容器网络和互补推挽放大器的开关电容放大器。 与使用单端A类放大器的开关电容放大器相比，本公开的开关电容放大器可以提供由电源提供并且在放大器的输出处流过放大器的电容性负载的较大部分电荷， 。 本公开的开关电容放大器可用于流水线模数转换器（ADC）的转换器级，以提高ADC的功率效率和/或带宽。 可以进一步推广使用流水线ADC以外的其他应用。

公开(公告)号：US20130201047A1

公开(公告)日：2013-08-08

申请号：US13566655

申请日：2012-08-03

申请人： Tsung-Heng TSAI ,  Pei-Jung HSU ,  Bo-Yu SHIU

发明人： Tsung-Heng TSAI ,  Pei-Jung HSU ,  Bo-Yu SHIU

IPC分类号： H03M1/12

CPC分类号： H03M1/1023 ,  H03M1/0682 ,  H03M1/164

摘要： A zero-crossing-based analog-to-digital converter having current mismatch correction capability, that can raise resolution, energy efficiency, and sampling rate of a fully differential zero-crossing circuit, is realized through a 90 nm CMOS technology. The circuit is used mainly to correct offset error, to use a current supply separation technology and a digital correction mechanism to correct mismatch among a plurality of current supplies.

摘要翻译： 通过90nm CMOS技术实现了具有电流失配校正能力的基于零交叉的模数转换器，其可以提高全差分过零电路的分辨率，能量效率和采样率。 该电路主要用于校正偏移误差，使用电流分配技术和数字校正机构来校正多个电流源之间的不匹配。

公开(公告)号：US08497789B2

公开(公告)日：2013-07-30

申请号：US13489962

申请日：2012-06-06

申请人： Daniel Meacham ,  Andrea Panigada ,  Jorge Grilo

发明人： Daniel Meacham ,  Andrea Panigada ,  Jorge Grilo

IPC分类号： H03M1/06

CPC分类号： H03M1/0673 ,  H03M1/0641 ,  H03M1/164

摘要： A pipeline ADC is provided in which a DEM function and summation of sequences occur within a flash ADC. According to various aspects of the present disclosure, embedding the processing functions needed for DAC and amplifier error correction with the circuitry of a coarse ADC and rearranging the digital calibration blocks HDC and DNC ensures accurate estimation of the errors.

摘要翻译： 提供了一种流水线ADC，其中在闪存ADC内发生DEM功能和序列求和。 根据本公开的各个方面，使用粗略ADC的电路嵌入DAC所需的处理功能和放大器误差校正，并重新排列数字校准块HDC和DNC可以准确估计误差。

公开(公告)号：US08487793B2

公开(公告)日：2013-07-16

申请号：US13242675

申请日：2011-09-23

申请人： Roger Petigny ,  Hugo Gicquel ,  Sophie Minot

发明人： Roger Petigny ,  Hugo Gicquel ,  Sophie Minot

IPC分类号： H03M1/06

CPC分类号： H03M1/1047 ,  H03M1/164

摘要： Device for processing an analogue signal, comprising an analogue-digital converter with a pipelined architecture having an offset, and compensation means configured to compensate for the said offset, the said compensation means comprising digital correction means configured to correct the integer portion of the offset based on the digital signal delivered by the analogue-digital converter, and analogue correction means included in the last stage of the analogue-digital converter and configured to correct the decimal portion of the offset.

摘要翻译： 用于处理模拟信号的装置，包括具有偏移的流水线架构的模拟数字转换器，以及被配置为补偿所述偏移的补偿装置，所述补偿装置包括数字校正装置，被配置为校正基于偏移的整数部分 对由模拟数字转换器传送的数字信号和模拟数字转换器的最后级中包括的模拟校正装置进行校正，并且被配置为校正偏移的小数部分。

公开(公告)号：US20130145066A1

公开(公告)日：2013-06-06

申请号：US13309664

申请日：2011-12-02

申请人： Bryan Kris

发明人： Bryan Kris

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  H03M1/06 ,  H03M1/1225 ,  H03M1/164 ,  H03M1/44

摘要： An early interrupt feature enables generation of interrupts prior to completion of an analog-to-digital conversion to be used in a processor PID calculation. Even though an analog-to-digital conversion is still in process, the PID application software can use the early interrupt time to begin execution of an interrupt service routine (ISR). The early interrupt can improve the throughput and response time of the PID control loop by overlapping the completion of the ADC conversion with the processor overhead associated with the interrupt request. A plurality of pipelined registers, each having substantially the same delay time as the pipelined stages of the ADC, are selectable to provided a delay time that may be used to generate an early interrupt, wherein the latency time between an ADC conversion and processing of an interrupt relating to that ADC conversion may thereby be shortened.

摘要翻译： 早期中断功能可以在完成模数转换之前产生中断，以在处理器PID计算中使​​用。 即使模数转换仍在进行中，PID应用软件可以使用早期中断时间来开始执行中断服务程序（ISR）。 早期中断可以通过将ADC转换的完成与与中断请求相关联的处理器开销重叠来提高PID控制环路的吞吐量和响应时间。 可以选择多个流水线寄存器，每个流水线寄存器具有与ADC的流水线阶段基本上相同的延迟时间，以提供可用于产生早期中断的延迟时间，其中ADC转换和处理 因此可以缩短与该ADC转换有关的中断。