发明授权
US08497789B2 Modified dynamic element matching for reduced latency in a pipeline analog to digital converter
有权
改进的动态元素匹配，以减少流水线模数转换器的延迟
- 专利标题： Modified dynamic element matching for reduced latency in a pipeline analog to digital converter
- 专利标题（中）： 改进的动态元素匹配，以减少流水线模数转换器的延迟
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申请号： US13489962申请日： 2012-06-06
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公开(公告)号： US08497789B2公开(公告)日： 2013-07-30
- 发明人: Daniel Meacham , Andrea Panigada , Jorge Grilo
- 申请人： Daniel Meacham , Andrea Panigada , Jorge Grilo
- 申请人地址： US AZ Chandler
- 专利权人： Microchip Technology Incorporated
- 当前专利权人： Microchip Technology Incorporated
- 当前专利权人地址： US AZ Chandler
- 代理机构： King & Spalding L.L.P.
- 主分类号： H03M1/06
- IPC分类号： H03M1/06
摘要：
A pipeline ADC is provided in which a DEM function and summation of sequences occur within a flash ADC. According to various aspects of the present disclosure, embedding the processing functions needed for DAC and amplifier error correction with the circuitry of a coarse ADC and rearranging the digital calibration blocks HDC and DNC ensures accurate estimation of the errors.
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