公开(公告)号：US09007251B2

公开(公告)日：2015-04-14

申请号：US13629220

申请日：2012-09-27

Applicant: Innovationszentrum fuer Telekommunikationstechnik GmbH IZT

Inventor： Rainer Perthold

IPC: H03M1/12 ,  H03M1/06 ,  G01R23/16

CPC classification number: H03M1/0678 ,  G01R23/16 ,  H03M1/121

Abstract: An apparatus for converting an analog signal into a digital signal includes: two identical analog-to-digital-converters converting the analog signal into first and second digital time domain signals; first and second transformation units transforming the first and second digital time domain signals into first and second digital frequency domain signals; a frequency compensation unit modifying the second frequency signal to reduce a difference between wanted signal components of the second and first frequency values caused by a difference between frequency responses of the analog-to-digital converters; a comparison unit determining for a same frequency bin corresponding first and second energy values associated to corresponding frequency values of the first and second digital frequency domain signal, and determining a minimum energy value thereof; and a selection unit selecting for a same frequency bin of the digital frequency domain signal the digital frequency domain signal associated to the minimum energy value.

Abstract translation: 一种用于将模拟信号转换为数字信号的装置包括：将模拟信号转换为第一和第二数字时域信号的两个相同的模 - 数转换器; 第一和第二变换单元将第一和第二数字时域信号变换为第一和第二数字频域信号; 频率补偿单元，修改所述第二频率信号以减少由所述模数转换器的频率响应之间的差引起的所述第二和第一频率值的有用信号分量之间的差; 比较单元确定与第一和第二数字频域信号的对应频率值相关联的相应频率仓对应的第一和第二能量值，并确定其最小能量值; 并且选择单元选择数字频域的相同频率仓信号与最小能量值相关联的数字频域信号。

公开(公告)号：US20150077278A1

公开(公告)日：2015-03-19

申请号：US14553598

申请日：2014-11-25

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Ian Juso Dedic ,  Gavin Lambertus Allen

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/08 ,  H03M1/00

CPC classification number: H03M1/0614 ,  G11C27/02 ,  H01H9/54 ,  H03K17/00 ,  H03L7/00 ,  H03L7/091 ,  H03M1/002 ,  H03M1/0881 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/126 ,  Y10T307/76

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract translation: 公开了被配置为由基本正弦时钟信号驱动的电流模式时间交织采样电路。 这种电路可以并入ADC电路中，例如作为IC芯片上的集成电路。 所公开的电路能够自行校准而不脱机。

公开(公告)号：US20140266826A1

公开(公告)日：2014-09-18

申请号：US13830826

申请日：2013-03-14

Applicant: THE AEROSPACE CORPORATION

Inventor： George C. VALLEY ,  George SEFLER ,  Thomas Justin SHAW

IPC: H03M1/12

CPC classification number: H03M1/12 ,  G02F7/00 ,  H03M1/121 ,  H03M1/1245

Abstract: Systems and methods for converting wideband signals into the digital domain are provided herein. The system may include an electronic or guided-wave optic based replicator configured to obtain at least M replicas of a signal applied thereto, and an electronic or guided-wave optic based segmenter configured to segment a signal applied thereto into at least N segments based on time or wavelength. Together, the replicator and the segmenter obtain M×N segment replicas of the received signal. An electronic or guided-wave optic based mixer is configured to multiply the M×N segment replicas by a mixing matrix having dimension M×N and then to form M integrations each of N segment replicas so as to obtain a measurement vector of length M. A signal recovery processor is configured to obtain a digital representation of the received signal based on the measurement vector and the mixing matrix.

Abstract translation: 本文提供了将宽带信号转换为数字域的系统和方法。 该系统可以包括基于电子或导波光学的复制器，其被配置为获得施加到其上的信号的至少M个复本，以及基于电子或导波光学器件的分段器，其被配置为基于至少N个段来施加到其上的信号 时间或波长。 复制器和分割器一起获得接收信号的M×N段复制。 电子或导波光学混合器被配置为将M×N段复制品乘以尺寸为M×N的混合矩阵，然后形成N个片段副本的M个积分，以获得长度为M的测量向量。 信号恢复处理器被配置为基于测量向量和混合矩阵来获得接收信号的数字表示。

公开(公告)号：US08581768B1

公开(公告)日：2013-11-12

申请号：US13535037

申请日：2012-06-27

Applicant: Christopher Pagnanelli

Inventor： Christopher Pagnanelli

IPC: H03M1/12

CPC classification number: H03M3/30 ,  H03M1/0836 ,  H03M1/121 ,  H03M3/468

Abstract: Provided is, among other things, an apparatus that includes an input line for accepting an input signal that is continuous in time and continuously variable. Multiple processing branches are coupled to the input line, each including: (a) an analog bandpass filter, (b) a sampling/quantization circuit coupled to an output of the analog bandpass filter, and (c) a digital bandpass filter coupled to an output of the sampling/quantization circuit. An adder is coupled to outputs of the processing branches. The digital bandpass filters in different ones of the processing branches have frequency response bandwidths that are centered at different frequencies, and the analog bandpass filters in different ones of the processing branches have frequency responses with bandwidths that are at least 25% greater than the frequency response bandwidths of the digital bandpass filters in their respective processing branches.

Abstract translation: 尤其提供一种装置，其包括用于接受在时间上连续且连续变化的输入信号的输入线。 多个处理分支耦合到输入线，每个分支包括：（a）模拟带通滤波器，（b）耦合到模拟带通滤波器的输出的采样/量化电路，以及（c）数字带通滤波器，耦合到 采样/量化电路的输出。 加法器耦合到处理分支的输出。 不同处理分支中的数字带通滤波器具有以不同频率为中心的频率响应带宽，并且不同处理分支中的模拟带通滤波器具有频带响应，带宽比频率响应大至少25％ 在其各自的处理分支中的数字带通滤波器的带宽。

公开(公告)号：US20130147647A1

公开(公告)日：2013-06-13

申请号：US13712522

申请日：2012-12-12

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Ian Juso DEDIC ,  Gavin Lambertus Allen

IPC: H03L7/00 ,  H03M1/12

CPC classification number: H03M1/0614 ,  G11C27/02 ,  H01H9/54 ,  H03K17/00 ,  H03L7/00 ,  H03L7/091 ,  H03M1/002 ,  H03M1/0881 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/126 ,  Y10T307/76

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

公开(公告)号：US20130106638A1

公开(公告)日：2013-05-02

申请号：US13666251

申请日：2012-11-01

Applicant: Marvell International Ltd.

Inventor： Sehat Sutardja ,  Giovanni Antonio Cesura ,  Francesco Rezzi ,  Rinaldo Castello

IPC: H03M1/12

CPC classification number: H03M1/20 ,  A01K79/00 ,  A23K50/80 ,  H03M1/002 ,  H03M1/0643 ,  H03M1/0678 ,  H03M1/1076 ,  H03M1/121 ,  H03M1/468

Abstract: A system including a clock generator configured to generate a clock; a plurality of analog-to-digital converters each configured to convert a signal based on the clock, and to output a first number of bits in response to converting the signal based on the clock; and an averaging module configured to receive the first number of bits from each of the plurality of analog-to-digital converters, and to output a second number of bits. The second number of bits is greater than the first number of bits.

Abstract translation: 一种包括被配置为产生时钟的时钟发生器的系统; 多个模数转换器，每个被配置为基于时钟转换信号，并且响应于基于时钟转换信号来输出第一位数; 以及平均模块，被配置为从所述多个模数转换器中的每一个接收所述第一数量的位，并输出第二数量的位。 第二位数大于第一位数。

公开(公告)号：US20130099948A1

公开(公告)日：2013-04-25

申请号：US13712740

申请日：2012-12-12

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Ian Juso DEDIC ,  Gavin Lambertus Allen

IPC: H03M1/12 ,  H01H9/54

CPC classification number: H03M1/0614 ,  G11C27/02 ,  H01H9/54 ,  H03K17/00 ,  H03L7/00 ,  H03L7/091 ,  H03M1/002 ,  H03M1/0881 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/126 ,  Y10T307/76

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

公开(公告)号：US20120041720A1

公开(公告)日：2012-02-16

申请号：US13282552

申请日：2011-10-27

Applicant: Peter James Pupalaikis ,  David Graef

Inventor： Peter James Pupalaikis ,  David Graef

IPC: G01R23/00

CPC classification number: H03M1/121 ,  G01R13/02 ,  G01R13/0272 ,  G01R19/25 ,  G06F17/40 ,  G06F19/00 ,  H03M1/60

Abstract: A method for improving bandwidth of an oscilloscope involves, in preferred embodiments, the use of frequency up-conversion and down-conversion techniques. In an illustrative embodiment the technique involves separating an input signal into a high frequency content and a low frequency content, down-converting the high frequency content in the analog domain so that it may be processed by the oscilloscope's analog front end, digitizing the low frequency content and the down-converted high frequency content, and forming a digital representation of the received analog signal from the digitized low frequency content and high frequency content.

Abstract translation: 在优选实施例中，用于提高示波器的带宽的方法涉及使用上变频和下变频技术。 在说明性实施例中，该技术涉及将输入信号分离成高频内容和低频内容，对模拟域中的高频内容进行下变频，使得其可以由示波器的模拟前端处理，数字化低频 内容和下变频高频内容，并且从数字化的低频内容和高频内容形成接收的模拟信号的数字表示。

公开(公告)号：US20110123192A1

公开(公告)日：2011-05-26

申请号：US12864739

申请日：2009-01-28

Applicant: Amir Rosenthal ,  Moshe Horowitz ,  Michael Fleyer ,  Yuval Shapira

Inventor： Amir Rosenthal ,  Moshe Horowitz ,  Michael Fleyer ,  Yuval Shapira

IPC: H04J14/00

CPC classification number: H04J14/08 ,  H03M1/121 ,  H04J14/02

Abstract: A scheme for reconstructing multiband signals that occupy a small part of a given broad frequency range under the constraint of a small number of sampling channels. The multirate sampling scheme (MRS) entails gathering samples at several different rates whose sum is significantly lower than the Nyquist sampling rate. The number of channels does not depend on any characteristics of a signal. The reconstruction method may or may not rely on the synchronization between different sampling channels. The scheme can be implemented easily with optical sampling systems. The optical pulses required for the under-sampling are generated by a combination of an electrical comb generator and an electro-absorption optical modulator

Abstract translation: 一种用于在少量采样通道的限制下重建占用给定宽频率范围的一小部分的多频带信号的方案。 多速率采样方案（MRS）需要以几个不同的速率收集样本，其总和明显低于奈奎斯特采样率。 信道数量不取决于信号的任何特性。 重建方法可以或可以不依赖于不同采样通道之间的同步。 该方案可以轻松实现光采样系统。 欠采样所需的光脉冲由电梳发生器和电吸收光调制器的组合产生

公开(公告)号：US20100253414A1

公开(公告)日：2010-10-07

申请号：US12686757

申请日：2010-01-13

Applicant: Ian J. Dedic ,  Gavin L. Allen

Inventor： Ian J. Dedic ,  Gavin L. Allen

IPC: H03K17/00

CPC classification number: H03M1/0614 ,  G11C27/02 ,  H01H9/54 ,  H03K17/00 ,  H03L7/00 ,  H03L7/091 ,  H03M1/002 ,  H03M1/0881 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/126 ,  Y10T307/76

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract translation: 公开了被配置为由基本正弦时钟信号驱动的电流模式时间交织采样电路。 这种电路可以并入ADC电路中，例如作为IC芯片上的集成电路。 所公开的电路能够自行校准而不脱机。