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    Semiconductor device having redundancy word lines
    23.
    发明授权
    Semiconductor device having redundancy word lines 有权

    公开(公告)号：US11756648B1

    公开(公告)日：2023-09-12

    申请号：US17692049

    申请日：2022-03-10

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Minari Arai

    IPC: G11C29/00 ,  G11C29/18 ,  G11C29/36 ,  G11C11/406 ,  G11C29/44 ,  G11C29/12

    CPC classification number: G11C29/785 ,  G11C11/40615 ,  G11C11/40622 ,  G11C29/18 ,  G11C29/36 ,  G11C29/44 ,  G11C2029/1202

    Abstract: Disclosed herein is an apparatus that includes first register circuits configured to store a first address, and a comparing circuit configured to compare the first address with a second address. The comparing circuit includes first and second circuit sections. In a first operation mode, the comparing circuit is configured to activate a match signal when the first circuit section detects that the first bit group of the first address matches with the third bit group of the second address and the second circuit section detects that the second bit group of the first address matches with the fourth bit group of the second address. In a second operation mode, the comparing circuit is configured to activate the match signal when the first circuit section detects that the first bit group matches with the third bit group regardless of the second and fourth bit groups.

    Memory device
    24.
    发明授权
    Memory device 有权

    公开(公告)号：US11749374B1

    公开(公告)日：2023-09-05

    申请号：US17677951

    申请日：2022-02-22

    Applicant: Winbond Electronics Corp.

    Inventor： Tzu-Yin Wei

    IPC: G11C7/10 ,  G11C29/46 ,  G11C29/12 ,  G11C29/36 ,  H03K19/173 ,  H03K19/20

    CPC classification number: G11C29/46 ,  G11C7/1039 ,  G11C29/1201 ,  G11C29/36 ,  H03K19/1737 ,  H03K19/20 ,  G11C2029/3602

    Abstract: A memory device includes a memory cell array, a data accessing circuit, a data bus inversion calculator, a multiplexer, and an output result judging circuit. The data accessing circuit performs a data write-in operation or a data read-out operation on the memory cell array. The data accessing circuit reads read-out data from the memory cell array. The data bus inversion calculator generates inversion indication data according to the read-out data. The multiplexer outputs the inversion indication data or test data according to a mode signal. The output result judging circuit compares the read-out data with the inversion indication data or the test data to generate output information.

    DEVICE FOR SUPPORTING ERROR CORRECTION CODE AND TEST METHOD THEREOF
    30.
    发明申请
    DEVICE FOR SUPPORTING ERROR CORRECTION CODE AND TEST METHOD THEREOF 审中-公开

    公开(公告)号：US20190088349A1

    公开(公告)日：2019-03-21

    申请号：US16135325

    申请日：2018-09-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Suk-soo PYO ,  Hyun-taek JUNG ,  Tae-joong SONG

    IPC: G11C29/42 ,  G06F11/10

    CPC classification number: G11C29/42 ,  G06F11/1044 ,  G06F11/2215 ,  G11C29/36 ,  G11C29/46 ,  G11C2029/0403

    Abstract: A device for supporting a test mode for memory testing according to an example embodiment of the inventive concepts may include a memory configured to receive and store writing data and output reading data from the stored writing data; an error correction code (ECC) engine configured to generate the writing data by encoding input data and to generate output data by correcting error bits of N bits or less included in receiving data when N is a positive integer; and an error insertion circuit configured to provide the reading data to the ECC engine as the receiving data in a normal mode and to provide data obtained by inverting at least one bit of less than N bits of the reading data to the ECC engine as the receiving data in the test mode.

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