公开(公告)号：US11217550B2

公开(公告)日：2022-01-04

申请号：US16044363

申请日：2018-07-24

申请人： Xilinx, Inc.

发明人： Jaspreet Singh Gandhi ,  Suresh Ramalingam

IPC分类号： H01L23/00 ,  H01L21/3065 ,  H01L21/78

摘要： An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is embodied in a wafer that includes a substrate having a plurality of integrated circuit (IC) dice formed thereon. The plurality of IC dice include a first IC die having first solid state circuitry and a second IC die having second solid state circuitry. A first contact pad is disposed on the substrate and is coupled to the first solid state circuitry. A first solder ball is disposed on the first contact pad. The first solder ball has a substantially uniform oxide coating formed thereon.

公开(公告)号：US10720377B2

公开(公告)日：2020-07-21

申请号：US16186178

申请日：2018-11-09

申请人： Xilinx, Inc.

发明人： Gamal Refai-Ahmed ,  Ho Hyung Lee ,  Hui-Wen Lin ,  Henley Liu ,  Suresh Ramalingam

IPC分类号： H01L29/40 ,  H01L23/40 ,  H01L23/48 ,  H01L23/00 ,  H01L23/427

摘要： Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener.

公开(公告)号：US20200035635A1

公开(公告)日：2020-01-30

申请号：US16044363

申请日：2018-07-24

申请人： Xilinx, Inc.

发明人： Jaspreet Singh Gandhi ,  Suresh Ramalingam

IPC分类号： H01L23/00 ,  H01L21/3065 ,  H01L21/78

摘要： An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is embodied in a wafer that includes a substrate having a plurality of integrated circuit (IC) dice formed thereon. The plurality of IC dice include a first IC die having first solid state circuitry and a second IC die having second solid state circuitry. A first contact pad is disposed on the substrate and is coupled to the first solid state circuitry. A first solder ball is disposed on the first contact pad. The first solder ball has a substantially uniform oxide coating formed thereon.

公开(公告)号：US10319606B1

公开(公告)日：2019-06-11

申请号：US15813008

申请日：2017-11-14

申请人： Xilinx, Inc.

发明人： Jaspreet Singh Gandhi ,  Tien-Yu Lee ,  Henley Liu ,  Ivor G. Barber ,  Suresh Ramalingam

IPC分类号： H01L23/48 ,  H01L23/498 ,  H05K1/11 ,  H01L21/48 ,  H01L23/00 ,  H01L23/50 ,  H01L23/14

摘要： An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a package substrate having a plurality of solder balls coupled to a plurality of contact pads. The package substrate includes a solder mask having a plurality of stepped openings, a plurality of contact pads, and circuitry disposed in the package substrate and coupled to the plurality of contact pads. The solder mask defines a top side of the package substrate. The stepped openings expose the contact pads through solder mask.

公开(公告)号：US10043730B2

公开(公告)日：2018-08-07

申请号：US14867349

申请日：2015-09-28

申请人： Xilinx, Inc.

发明人： Gamal Refai-Ahmed ,  Tien-Yu Lee ,  Ferdinand F. Fernandez ,  Suresh Ramalingam ,  Ivor G. Barber ,  Inderjit Singh ,  Nael Zohni

IPC分类号： H01L23/10 ,  H01L23/367 ,  H01L25/065 ,  H01L23/373 ,  H01L25/00 ,  H01L23/16 ,  H01L25/18 ,  H01L23/04 ,  H01L23/473 ,  H01L21/48 ,  H01L23/00 ,  H01L23/40

摘要： A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.

公开(公告)号：US12027493B2

公开(公告)日：2024-07-02

申请号：US16672802

申请日：2019-11-04

申请人： XILINX, INC.

发明人： Jaspreet Singh Gandhi ,  Suresh Ramalingam

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/60 ,  H01L23/00

CPC分类号： H01L25/0655 ,  H01L21/565 ,  H01L24/05 ,  H01L2021/60007 ,  H01L2224/02371 ,  H01L2224/02372

摘要： A chip package assembly and method for fabricating the same are provided which utilize a plurality of posts in mold compound for improved resistance to delamination. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die, a substrate, a redistribution layer, a mold compound and a plurality of posts. The redistribution layer provides electrical connections between circuitry of the first IC die and circuitry of the substrate. The mold compound is disposed in contact with the first IC die and spaced from the substrate by the redistribution layer. The plurality of posts are disposed in the mold compound and are laterally spaced from the first IC die. The plurality of posts are not electrically connected to the circuitry of the first IC die.

公开(公告)号：US11605886B1

公开(公告)日：2023-03-14

申请号：US17133518

申请日：2020-12-23

申请人： XILINX, INC.

发明人： Gamal Refai-Ahmed ,  Chi-Yi Chao ,  Lik Tsang ,  Jens Weis ,  Brendan Farley ,  Anthony Torza ,  Suresh Ramalingam

IPC分类号： H01Q1/42 ,  H01L23/427 ,  H01Q1/02

摘要： An antenna assembly is provided having passive cooling elements that enable compact design. In one example, an antenna assembly is provided that includes a heat sink assembly having an interior side and an exterior side, an antenna array, an antenna circuit board, and a radome. The antenna circuit board includes at least one integrated circuit (IC) die. The IC die has a conductive primary heat dissipation path to the interior side of the heat sink assembly. The radome is coupled to the heat sink assembly and encloses the antenna circuit board and the antenna array between the radome and the heat sink assembly. The heat sink assembly includes a metal base plate and at least a first heat pipe embedded with the metal base plate. The first heat pipe is disposed between the metal base plate and the IC die.

公开(公告)号：US11488936B2

公开(公告)日：2022-11-01

申请号：US16718868

申请日：2019-12-18

申请人： Xilinx, Inc.

发明人： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Cheang-Whang Chang

IPC分类号： H01L25/065 ,  H01L23/367 ,  H01L23/04 ,  H01L23/31

摘要： A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.

公开(公告)号：US11488887B1

公开(公告)日：2022-11-01

申请号：US16810473

申请日：2020-03-05

申请人： XILINX, INC.

发明人： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Boon Y. Ang ,  Toshiyuki Hisamura ,  Suresh Parameswaran ,  Scott McCann ,  Hoa Lap Do

IPC分类号： H01L23/367 ,  H01L21/306 ,  H01L23/00 ,  H01L23/373

摘要： In one example, a method includes providing a first side of a semiconductor substrate with a plurality of transistors, etching a second side of the substrate, opposite the first side, with a pattern of trenches, the trenches having a pre-defined depth and width, and providing the etched semiconductor substrate in a package. In one example, the predefined depth and width of the trenches is such so as to increase the surface area of the second side of the substrate by at least 20 percent. In one example, the method also includes providing a layer of a thermal interface material (TIM) on the second side of the substrate, including to fill at least a portion of the trenches.

公开(公告)号：US11195780B1

公开(公告)日：2021-12-07

申请号：US16828822

申请日：2020-03-24

申请人： XILINX, INC.

发明人： Jaspreet Singh Gandhi ,  Gamal Refai-Ahmed ,  Suresh Ramalingam

IPC分类号： H01L31/12 ,  H01L23/427 ,  H01L23/373 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/10

摘要： A chip package assembly and method for fabricating the same are provided which incorporate phase change materials within the chip package assembly for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die stacked on the substrate, a dielectric filler layer, a cover and a phase change material. The phase change material is sealed within a recess formed between the first IC dies and the cover.