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公开(公告)号：US10657918B2
公开(公告)日：2020-05-19
申请号：US15327303
申请日：2016-12-30
Inventor： Yafeng Li
IPC: G09G3/36
Abstract: Disclosed is a gate driving circuit and a display device, which belongs to the technical field of displaying, and resolves a technical problem that a signal transmitted between cascaded gate driving circuits is easily attenuated in the prior art. The gate driving circuit includes a precharging unit circuit, an output unit circuit, and a compensation charging unit circuit; the output unit circuit includes a first reference point and a first clock signal line; and the precharging unit circuit is configured to input a high level to the first reference point before an output period.
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公开(公告)号：US10484655B2
公开(公告)日：2019-11-19
申请号：US15327301
申请日：2016-12-30
Inventor： Yafeng Li
IPC: H04N9/30 , G02F1/1345 , G09G3/36
Abstract: Disclosed is a gate driving circuit and a display device, which solve the technical problem that the prior art is easy to cause abnormal output of gate driving signals. The gate driving circuit includes a precharge unit circuit, an output unit circuit, and a holding unit circuit. The output unit circuit includes a first reference point and a clock signal line. The holding unit circuit includes a second reference point and a holding signal line, and a holding capacitor is connected between the second reference point and the holding signal line.
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公开(公告)号：US10460652B2
公开(公告)日：2019-10-29
申请号：US15312197
申请日：2016-09-18
Inventor： Yafeng Li
IPC: G09G3/3208 , G09G3/36
Abstract: The present application discloses a scanning driving circuit and a flat display apparatus, the scanning driving circuit includes a plurality of cascaded scanning driving unit, each scanning driving unit including a forward and reverse scanning circuit for controlling the forward or reverse scanning; an input circuit to perform charging to the pull-up control signal point and the pull-down control signal point; an output circuit for generating a scanning driving signal with two-valued high electrical level and outputting to the current level scanning line to drive a pixel unit.
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公开(公告)号：US10290262B2
公开(公告)日：2019-05-14
申请号：US15304497
申请日：2016-09-18
Inventor： Yafeng Li
IPC: G09G3/3266 , G09G3/36 , G09G3/20 , G11C19/28
Abstract: The present disclosure provides a scanning drive circuit and a flat display device, the scanning drive circuit includes a plurality of cascaded scanning driving units, each scanning driving unit includes a forward-reverse scanning circuit used to control the forward scan and the reverse scan; a input circuit used to charge the pull-up and pull-down control signal point; a charge compensating circuit used to compensating charge the pull-up and pull-down control signal point; a output circuit generating the scanning driving signal to the present scanning line driving the pixel unit.
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公开(公告)号：US10255869B2
公开(公告)日：2019-04-09
申请号：US15506240
申请日：2016-12-30
Inventor： Yafeng Li
Abstract: The present invention relates to a GOA circuit. The GOA circuit comprises: a first thin film transistor (T1) to a fourteenth thin film transistor (T14), a first capacitor (C1) and a second capacitor (C2). The present invention adds a control unit consisted of thin film transistors (T9-T14) on the basis of the GOA circuit structure according to prior art, and a set of control signals (Select1, Select2) of which phases are opposite is introduced. The main function is to divide the gate output of the GOA circuit into two. In some special display mode, the frequency corresponded with Data signal will be halved, and the corresponding drive power consumption will be decreased. The present invention provides a GOA circuit, which can effectively reduce the layout space occupied by the GOA circuit for having a certain help to the development of the narrow frame technology.
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Patent Agency Ranking
公开(公告)号：US10170067B2
公开(公告)日：2019-01-01
申请号：US15308843
申请日：2016-06-13
Inventor： Yafeng Li
IPC: G09G3/36 , G02F1/1345 , G02F1/1362 , G02F1/1368 , H01L27/12
Abstract: A GOA electric circuit introduces a resistor and a timing signal, which are used to replace a second capacitor in the existing skills. One terminal of the resistor is connected to a constant high voltage level and the other terminal thereof is connected to a gate electrode of a ninth thin-film transistor. A source electrode of the ninth thin-film transistor is electrically connected to the timing signal. In the stage maintaining the output terminal at low voltage level, the voltage level of the second node can be changed between high and low voltage levels as the timing signal is changed, and the voltage level of the second node is pulled down in a specific frequency. This effectively prevents the second node from being at high voltage level for a long time and avoids the problem of threshold voltage shifting, and therefore improves the stability of GOA electric circuit.
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公开(公告)号：US10126343B2
公开(公告)日：2018-11-13
申请号：US14912924
申请日：2016-01-29
Inventor： Yafeng Li , Xiangyi Peng
IPC: G01R31/00 , G01R31/08 , G02F1/1362 , G02F1/1368 , G09G3/00 , G02F1/1333 , G09G3/36
Abstract: The invention provides an ESD detection method for array substrate. By connecting the first metal layer on array substrate through the first wire to the first test point, connecting the second metal layer on array substrate through the second wire to the second test point, when ESD occurs on array substrate, the resistance detection device is used to measure the resistance between the first and second test points. If the resistance is positive infinity, ESD did not occur between the first and second metal layers; if the resistance is within a measurable range, ESD occurs between the first and second metal layers. The resistance is used to locate the location of ESD occurrence on array substrate. Compared to known method using microscope to search ESD location, the invention can locate ESD location on array substrate more accurately and rapidly to save time and labor as well as detection cost.
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公开(公告)号：US20180218686A1
公开(公告)日：2018-08-02
申请号：US15506237
申请日：2016-12-30
Inventor： Yafeng Li
IPC: G09G3/3266 , G09G3/36 , G09G3/3258
CPC classification number: G09G3/3266 , G09G3/3258 , G09G3/3648 , G09G3/3677 , G09G3/3696 , G09G2300/0408 , G09G2310/0283 , G09G2310/08 , G09G2320/0214 , G11C19/184 , G11C19/28
Abstract: The invention provides a GOA circuit, comprising a plurality of GOA units, for a positive integer n, n-th GOA unit comprising: a first TFT (T1), a second TFT (T2), a third TFT (T3), a fourth TFT T(4), a fifth TFT (T5), a sixth TFT (T6), a seventh TFT (T7), an eighth TFT (T8), a ninth TFT (T9), a tenth TFT (T10), a first capacitor (C1) and a second capacitor (T2). The invention, based on known GOA circuit, uses T9 and T10 so as to achieve forward and backward scanning without D2U and U2D control signals, which facilitates narrow border design and simplifies corresponding driving timing and reduce IC cost. The pre-charging unit formed by T1, T9, T3, and T10 effectively improves the current leakage and ensures GOA circuit stability.
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公开(公告)号：US20180033712A1
公开(公告)日：2018-02-01
申请号：US14914655
申请日：2016-01-28
Inventor： Yafeng Li , Xiangyi Peng
IPC: H01L23/34 , H01L29/786 , H01L27/12
CPC classification number: H01L23/345 , G02F1/133382 , G02F1/136209 , G02F1/1368 , G02F2202/104 , H01L27/1222 , H01L27/124 , H01L27/1255 , H01L29/78633 , H01L29/78672
Abstract: The invention provides an array substrate and activation method for TFT elements in the array substrate. The array substrate comprises a shielding metal layer (10) and a TFT layer (20) disposed on the shielding metal layer (10); by connecting the shielding metal blocks (11) on the shielding metal layer (10) to electricity to heat up the shielding metal blocks (11) for pre-heating the TFT layer (20) to accelerate activating the TFT elements in the TFT layer (20). The activation method, by connecting the shielding metal blocks (11) on the shielding metal layer (10) to electricity to heat up the shielding metal blocks (11) for pre-heating the TFT layer (20) before activating the TFT elements in the TFT layer (20), accelerates activating the TFT elements in the TFT layer (20). The method is applicable to activating the TFT elements in array substrate in low temperature environment.
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公开(公告)号：US20170301303A1
公开(公告)日：2017-10-19
申请号：US14917572
申请日：2016-01-28
Inventor： Yafeng Li
IPC: G09G3/36 , H01L29/786 , H01L27/12
CPC classification number: G09G3/3677 , G09G3/36 , G09G2300/0408 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291 , G09G2310/08 , H01L27/1222 , H01L27/124 , H01L27/1255 , H01L29/78672
Abstract: The invention provides a GOA circuit for LTPS-TFT, using a resistor (R1) and a tenth TFT (T10) to replace the second capacitor in known technology, and change the diode-style connection of the ninth TFT (T9) in known technology to connect one end of the resistor (R1) to the constant high voltage (VGH) and the other to the gate of the ninth TFT (T9) so that during the output end (G(n)) staying at low, the voltage of the second node (P(n)) follows the (M+1)-th clock signal (CK(M+1)) to switch between high and low, that is, following a fixed frequency to pull down the voltage of the second node (P(n)), prevents the second node from staying at high for long duration and prevents the sixth TFT (T6) and the seventh TFT (T7) from prolonged operation to cause threshold voltage shift and improve GOA circuit stability.
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