公开(公告)号：US5457788A

公开(公告)日：1995-10-10

申请号：US992281

申请日：1992-12-16

Applicant: Hirohisa Machida

Inventor： Hirohisa Machida

IPC: G06F12/08 ,  G06F12/10 ,  G11C15/00 ,  G11C15/04 ,  G06F12/02

CPC classification number: G11C15/04 ,  G06F12/1054

Abstract: An associative memory system using an associative memory circuit, capable of performing hit judgment on cache data at a high speed. The associative memory system comprises a virtual-address holding CAM circuit 2 for outputting a hit signal 5 when the data previously stored in a supplied address coincides with a supplied virtual address 4, a cache-tag memory circuit 1 for outputting cache-tag data coinciding with the supplied virtual address 4 when the data is present, and a physical-address holding CAM circuit 3 which connects with an output line for outputting the hit signal 5 given from the CAM circuit 2 and outputs the hit signal 6 when a physical address previously stored in the memory area from which the hit signal is outputted coincides with cache tag data supplied from the cache-tag memory circuit 1.

Abstract translation: 一种使用关联存储器电路的关联存储器系统，其能够高速地对高速缓存数据执行命中判断。 关联存储器系统包括虚拟地址保持用CAM电路2，用于当预先存储在所提供的地址中的数据与所提供的虚拟地址4一致时输出命中信号5，高速缓存标签存储电路1用于输出一致的高速缓存标签数据 当存在数据时提供的虚拟地址4，以及物理地址保持CAM电路3，其与用于输出从CAM电路2给出的命中信号5的输出线连接，并且当先前的物理地址输出时，输出命中信号6 存储在从其输出命中信号的存储区域与从高速缓存标签存储器电路1提供的缓存标签数据一致。

公开(公告)号：US5339268A

公开(公告)日：1994-08-16

申请号：US980865

申请日：1992-11-24

Applicant: Hirohisa Machida

Inventor： Hirohisa Machida

IPC: G11C15/04 ,  G06F12/08 ,  G06F12/12 ,  G11C15/00

CPC classification number: G11C15/00 ,  G06F12/123

Abstract: A content addressable memory circuit includes a plurality of CAM cell circuits provided in a matrix of rows and columns, a matching line arranged corresponding to each row, and a rewrite control circuit for generating a rewrite instruct signal according to a signal on the matching line. The CAM cell circuit includes a master memory portion for storing a reference data to be compared, a slave memory portion for storing data of an adjacent word, transfer element for transferring to the master memory portion the data stored in the slave memory portion according to a rewrite instruct signal from the rewrite control circuit, and a comparison/driving portion for comparing an input data transmitted to a bit line with the data stored in the master memory portion to drive an associated matching line according to the comparison result. The stored data in the CAM cell circuit is updated according to a shifting operation. The input data is stored in the CAM cell circuit of a certain address. The least recently accessed data is always stored in the CAM cell circuit of another certain address. A content addressable memory circuit is obtained that executes LRU algorithm at a high speed.

Abstract translation: 内容可寻址存储电路包括以行和列为矩阵设置的多个CAM单元电路，对应于每行布置的匹配线，以及根据匹配线上的信号产生重写指示信号的重写控制电路。 CAM单元电路包括用于存储要比较的参考数据的主存储器部分，用于存储相邻字的数据的从存储器部分，用于根据存储在主存储器部分中的数据传送到主存储器部分的传送元件 重写控制电路的重写指令信号，以及比较/驱动部分，用于将发送到位线的输入数据与存储在主存储器部分中的数据进行比较，以根据比较结果驱动相关匹配线。 根据移位操作更新CAM单元电路中存储的数据。 输入数据存储在特定地址的CAM单元电路中。 最近访问的数据总是存储在另一个特定地址的CAM单元电路中。 获得以高速执行LRU算法的内容可寻址存储电路。

公开(公告)号：US5323347A

公开(公告)日：1994-06-21

申请号：US832570

申请日：1992-02-07

Applicant: Hirohisa Machida

Inventor： Hirohisa Machida

IPC: G06F7/38 ,  G06F7/50 ,  G06F7/503 ,  G06F7/506 ,  G06F15/78 ,  G06F17/10 ,  G11C7/10 ,  H03M7/02 ,  G11C7/00

CPC classification number: G06F7/503 ,  G11C7/1006 ,  H03M7/02

Abstract: A semiconductor memory device 1 includes a plurality of memory circuits 10. Each of the memory circuits 10 includes a data bit memory cell 11, a sign bit memory cell 12, a converting circuit 13 and a selecting circuit 14. The data bit memory cell 11 stores one bit of binary number data or a data bit of redundant binary number data. The sign bit memory cell 12 stores a digit of a sign bit of redundant binary number data. The converting circuit 13 converts redundant binary number data into binary number data on the basis of the data bit stored in the data bit memory cell and the sign bit stored in the sign bit memory cell 12. The selecting circuit 14 selects the data bit stored in data bit memory cell 11 or the one bit of binary number data outputted by the converting circuit 13.

Abstract translation: 半导体存储器件1包括多个存储电路10.每个存储电路10包括数据位存储单元11，符号位存储单元12，转换电路13和选择电路14.数据位存储单元11 存储一位二进制数字数据或冗余二进制数数据的数据位。 符号位存储单元12存储冗余二进制数数据的符号位的数字。 转换电路13基于存储在数据位存储单元中的数据位和存储在符号位存储单元12中的符号位，将冗余二进制数数据转换为二进制数数据。选择电路14选择存储在 数据位存储单元11或由转换电路13输出的二进制数数据的一位。