公开(公告)号：US20160190349A1

公开(公告)日：2016-06-30

申请号：US14583291

申请日：2014-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Tsu-Hui Su ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L29/792 ,  H01L29/423 ,  H01L21/02 ,  H01L29/16 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L21/02247 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

Abstract: The present disclosure relates to a structure and method for reducing dangling bonds around quantum dots in a memory cell. In some embodiments, the structure has a semiconductor substrate having a tunnel dielectric layer disposed over it and a plurality of quantum dots disposed over the tunnel dielectric layer. A passivation layer is formed conformally over outer surfaces of the quantum dots and a top dielectric layer is disposed conformally around the passivation layer. The passivation layer can be formed prior to forming the top dielectric layer over the quantum dots or after forming the top dielectric layer. The passivation layer reduces the dangling bonds at an interface between the quantum dots and the top dielectric layer, thereby preventing trap sites that may hinder operations of the memory cell.

Abstract translation: 本公开涉及用于减少存储单元中的量子点周围的悬挂键的结构和方法。 在一些实施例中，该结构具有其上设置有隧道介电层的半导体衬底和设置在隧道介电层上的多个量子点。 钝化层在量子点的外表面上保形地形成，并且顶部介电层被保形地设置在钝化层周围。 钝化层可以在形成量子点之前的顶部电介质层之后或在形成顶部电介质层之后形成。 钝化层减少量子点和顶部电介质层之间的界面处的悬挂键，从而防止可能阻碍存储单元操作的陷阱位置。

公开(公告)号：US20150311300A1

公开(公告)日：2015-10-29

申请号：US14261539

申请日：2014-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Tsu-Hui Su ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ru-Liang Lee

IPC: H01L29/423 ,  H01L29/792 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L21/02271 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42332

Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a tunnel oxide is formed over a semiconductor substrate. A layer of silicon dot nucleates is formed on the tunnel oxide. The layer of silicon dots includes silicon dot nucleates having respective initial sizes which differ according to a first size distribution. An etching process is performed to reduce the initial sizes of the silicon dot nucleates so reduced-size silicon dot nucleates have respective reduced sizes which differ according to a second size distribution. The second size distribution has a smaller spread than the first size distribution.

Abstract translation: 本公开的一些实施例涉及用于形成快闪存储器的方法。 在该方法中，在半导体衬底上形成隧道氧化物。 在隧道氧化物上形成一层硅点成核。 硅点层包括具有根据第一尺寸分布而不同的各自的初始尺寸的硅点成核。 进行蚀刻处理以减小硅点成核的初始尺寸，因此尺寸减小的硅点成核具有根据第二尺寸分布而不同的相应减小的尺寸。 第二尺寸分布具有比第一尺寸分布更小的扩展。