公开(公告)号：US11264300B2

公开(公告)日：2022-03-01

申请号：US16182750

申请日：2018-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Lin ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Chin-Hua Wang

IPC: H01L23/367 ,  H01L25/18 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00

Abstract: A package structure and method for forming the same are provided. The package structure includes a semiconductor die formed over a first side of an interconnect structure, and the semiconductor die has a first height. The package structure also includes a first stacked die package structure formed over the first side of the interconnect structure, and the first stacked die package structure has a second height. The second height is greater than the first height. The package structure includes a lid structure formed over the semiconductor die and the first stacked die package structure. The lid includes a main portion and a protruding portion extending from the main portion, and the protruding portion is directly over the semiconductor die.

公开(公告)号：US10163816B2

公开(公告)日：2018-12-25

申请号：US15180404

申请日：2016-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Chin-Hua Wang ,  Kuang-Chun Lee ,  Po-Yao Lin ,  Shyue-Ter Leu ,  Shin-Puu Jeng

IPC: H01L23/10 ,  H01L23/04 ,  H01L23/00 ,  H01L23/498 ,  H01L23/367

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over a surface of the substrate. The chip package also includes a lid over the semiconductor die. The lid has a number of support structures bonded with the substrate, and the lid has one or more openings between two of the support structures.

公开(公告)号：US09748156B1

公开(公告)日：2017-08-29

申请号：US15180264

申请日：2016-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Shen Yeh ,  Cheng-Lin Huang ,  Chin-Hua Wang ,  Kuang-Chun Lee ,  Wen-Yi Lin ,  Ming-Chih Yew ,  Yu-Huan Chen ,  Po-Yao Lin ,  Shyue-Ter Leu ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/18 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/18 ,  H01L23/16 ,  H01L23/3128 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00014

Abstract: A semiconductor package includes a cover, a substrate, at least one semiconductor device and at least one corner stiffener. The cover has at least one corner portion. The substrate is in force communication with the cover. The substrate has at least one corner portion. The semiconductor device is present between the cover and the substrate. The corner stiffener is present on at least one of the corner portion of the cover and the corner portion of the substrate.