公开(公告)号：US20190393106A1

公开(公告)日：2019-12-26

申请号：US16015965

申请日：2018-06-22

Applicant: Texas Instruments Incorporated

Inventor： Jaimal Mallory Williamson ,  Ethan Tilden Davis

IPC: H01L21/66 ,  H01L21/48 ,  H01L23/498 ,  G01R31/28

Abstract: Described examples provide a method to evaluate reliability of hail grid array products in which an interconnect stress test is performed that passes current through outer layer micro-vias of a test coupon portion of a production panel that is soldered to a printed circuit board, and the reliability of ball grid array products manufactured using package substrate portions of the production panel is evaluated according to the results of the interconnect stress test. A test coupon includes a rigid core material layer, dielectric layers laminated between copper layers above and below the core material layer, conductive micro-vias that extend through at least one of the dielectric layers between two of the copper layers, and conductive land pads on an outer one of the dielectric layers, the conductive land pads individually contacting one of the micro-vias.

公开(公告)号：US20180096859A1

公开(公告)日：2018-04-05

申请号：US15282534

申请日：2016-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaimal Mallory Williamson ,  Bernardo Gallegos ,  Jose Carlos Arroyo

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L21/4832 ,  H01L21/4821 ,  H01L21/4825 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/4951 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49586 ,  H01L23/49861 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A lead frame that is partially covered with an adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame and using a photo-imageable polyimide or epoxy material to form the adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame blank and using a photo-imageable polyimide or epoxy material to form the adhesion layer.

公开(公告)号：US20140138822A1

公开(公告)日：2014-05-22

申请号：US13682576

申请日：2012-11-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaimal Mallory Williamson ,  Nima Shahidi ,  Yaoyu Pang

IPC: H01L23/498

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/014

Abstract: An integrated circuit (IC) package, device, including a substrate having a top surface with an IC die mounting area and a peripheral area surrounding the mounting area, a plurality of parallel conductor layers, a plurality of insulating layers and a plurality of plated through holes (PTHs) extending through the conductor layers and insulating layers. Various substrate structures in which certain of the PTHs and/or conductor layers and/or insulating layers have different CTE's than the others is disclosed. The various structures may reduce circuit failures due to substrate warpage and/or solder joint damage associated with a CTE mismatch between the substrate and the IC die.

Abstract translation: 一种集成电路（IC）封装，包括具有具有IC管芯安装区域的顶表面和围绕安装区域的周边区域的衬底的器件，多个平行导体层，多个绝缘层和多个电镀通孔 延伸穿过导体层和绝缘层的孔（PTH）。 公开了其中某些PTH和/或导体层和/或绝缘层具有与其它层不同的CTE的各种衬底结构。 由于与基板和IC芯片之间的CTE失配相关联的基板翘曲和/或焊点损伤，各种结构可能减少电路故障。