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    LITHOGRAPHY MODEL CALIBRATION
    21.
    发明申请
    LITHOGRAPHY MODEL CALIBRATION 审中-公开

    公开(公告)号：US20200278604A1

    公开(公告)日：2020-09-03

    申请号：US16748551

    申请日：2020-01-21

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Shih-Hsiang LO ,  Hsu-Ting HUANG ,  Ru-Gun LIU

    IPC分类号： G03F1/36 ,  G03F1/00 ,  G03F1/70 ,  G03F7/20 ,  H01L21/027

    摘要： Provided is a method for fabricating a semiconductor device including generating an ideal image using measured contour data and fitted conventional model terms. The method further includes using the fitted conventional model terms and a mask layout to provide a conventional model aerial image. In some embodiments, the method further includes generating a plurality of mask raster images using the mask layout, where the plurality of mask raster images is generated for each measurement site of the measured contour data. In various embodiments, the method also include training a neural network to mimic the ideal image, where the generated ideal image provides a target output of the neural network, and where the conventional model aerial image and the plurality of mask raster images provide inputs to the neural network.

    LANDING METAL ETCH PROCESS FOR IMPROVED OVERLAY CONTROL
    22.
    发明申请
    LANDING METAL ETCH PROCESS FOR IMPROVED OVERLAY CONTROL 审中-公开

    公开(公告)号：US20200176267A1

    公开(公告)日：2020-06-04

    申请号：US16688681

    申请日：2019-11-19

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Chih-Min HSIAO ,  Chih-Ming LAI ,  Chien-Wen LAI ,  Ya Hui CHANG ,  Ru-Gun LIU

    IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

    摘要： A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

    PELLICLE STRUCTURE FOR LITHOGRAPHY MASK
    23.
    发明申请
    PELLICLE STRUCTURE FOR LITHOGRAPHY MASK 审中-公开

    公开(公告)号：US20200174382A1

    公开(公告)日：2020-06-04

    申请号：US16697138

    申请日：2019-11-26

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Shih-Ming CHANG ,  Chiu-Hsiang CHEN ,  Ru-Gun LIU ,  Minfeng CHEN

    IPC分类号： G03F7/20 ,  G03F1/64

    摘要： A lithography patterning system includes a reticle having patterned features, a pellicle having a plurality of openings, a radiation source configured for emitting radiation to reflect and/or project the patterned features, and one or more mirrors configured for guiding reflected and/or projected patterned features onto a wafer. The pellicle is configured to protect the reticle against particles and floating contaminants. The plurality of openings include between 5% and 99.9% of lateral surface area of the pellicle. The pellicle can be attached to the reticle on a side of the patterned features, placed beside an optical path between the radiation source and the wafer, or placed in an optical path between mirrors and the radiation source. The plurality of openings in the pellicle are formed by a plurality of bar shaped materials, or formed in a honey comb structure or a mesh structure.

    DESIGNED-BASED INTERCONNECT STRUCTURE IN SEMICONDUCTOR STRUCTURE
    30.
    发明申请
    DESIGNED-BASED INTERCONNECT STRUCTURE IN SEMICONDUCTOR STRUCTURE 有权
    半导体结构中基于设计的互连结构

    公开(公告)号：US20160064322A1

    公开(公告)日：2016-03-03

    申请号：US14476349

    申请日：2014-09-03

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chih-Liang CHEN ,  Chih-Ming LAI ,  Yung-Sung YEN ,  Kam-Tou SIO ,  Tsong-Hua OU ,  Chun-Kuang CHEN ,  Ru-Gun LIU ,  Shu-Hui SUNG ,  Charles Chew-Yuen YOUNG

    IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L27/118

    CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate and a contact formed adjacent to the gate structures over the substrate. The semiconductor structure further includes a plurality of metal layers formed over the gate structures. In addition, some of the metal layers include metal lines extending in the first direction, and some of the metal layers include metal lines extending in a second direction substantially perpendicular to the first direction. Furthermore, the gate structures follow the following equation: 0.2   P gate   min + 0.35   L gate   min + 0.3   H gate   min - 20 0.2   L gate   min + 0.8   H gate   min - 5 × 0.3   L gate   min + 0.3   H gate   min + 5 38 ≤ 0.32 Pgate min is the minimum value among gate pitches of the gate structures. Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.

    摘要翻译： 提供半导体结构。 半导体结构包括沿着形成在衬底上的第一方向延伸的多个栅极结构以及与衬底上的栅极结构相邻形成的触点。 半导体结构还包括形成在栅极结构上的多个金属层。 此外，一些金属层包括在第一方向上延伸的金属线，并且一些金属层包括沿基本上垂直于第一方向的第二方向延伸的金属线。 此外，栅极结构遵循以下公式：0.2P门min + 0.35min min min H门槛最小 - 5×0.3L门min + 0.3H门min + 5 38≤0.32 P门min是门结构的栅间距中的最小值。 Lgate min是门结构的栅极长度之间的最小值。 Hgate min是门结构栅极高度的最小值。