公开(公告)号：US11508420B2

公开(公告)日：2022-11-22

申请号：US17355765

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Lee ,  Daesik Moon ,  Young-Soo Sohn ,  Young-Hoon Son ,  Ki-Seok Oh ,  Changkyo Lee ,  Hyun-Yoon Cho ,  Kyung-Soo Ha ,  Seokhun Hyun

IPC: G11C7/10 ,  G06F3/06 ,  G11C29/02 ,  G11C29/50

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

公开(公告)号：US10885950B2

公开(公告)日：2021-01-05

申请号：US16363077

申请日：2019-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Kyung-Soo Ha ,  Young-Soo Sohn ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Jin-Hoon Jang ,  Yeon-Kyu Choi ,  Seok-Hun Hyun

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US10692555B2

公开(公告)日：2020-06-23

申请号：US16249594

申请日：2019-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Seok Oh ,  Seong-Hwan Jeon

IPC: G11C8/18 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/4076 ,  G11C29/12 ,  G11C29/02 ,  G11C29/10 ,  G11C8/12

Abstract: A method of operating a semiconductor memory device including a plurality of pins configured to transfer data and signals from/to an outside of the semiconductor memory device, a memory cell array and a control logic circuit to control access to the memory cell array. A write command synchronized with a main clock signal and data synchronized with a data clock signal are received from outside of the semiconductor memory device, the data is stored in the memory cell array based on a frequency-divided data clock signal, data is read from the memory cell array in response to a read command and a target address received from the outside of the semiconductor memory device, and the read data is transmitted to the outside of the semiconductor memory device selectively with a strobe signal generated based on a frequency of the main clock signal.

公开(公告)号：US10474593B2

公开(公告)日：2019-11-12

申请号：US16006082

申请日：2018-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghyun Kim ,  Ki-Seok Oh

IPC: G06F13/16 ,  G11C7/10 ,  G06F13/40 ,  G06F3/06 ,  H01L25/065

Abstract: An electronic device includes a memory and a system on chip (SoC). The memory device includes a first memory cell area assigned to a first channel and a second memory cell area assigned to a second channel. The SoC includes a first processing unit and a second processing unit. The first processing unit is configured to transmit a first command for accessing the first memory cell area to the memory device through the first channel. The second processing unit is configured to transmit a second command for accessing the second memory cell area to the memory device through the second channel. The memory device is configured such that a bandwidth of the first channel and a bandwidth of the second channel are different from each other.