公开(公告)号：US20240213302A1

公开(公告)日：2024-06-27

申请号：US18394644

申请日：2023-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin PARK ,  Hanjin LIM ,  Hyungsuk JUNG

IPC: H01G4/08

CPC classification number: H01L28/40 ,  H10B12/315

Abstract: An integrated circuit device may include a transistor on a substrate and a capacitor structure electrically connected to the transistor. The capacitor structure may include a first electrode, a dielectric layer structure on the first electrode, and a second electrode on the dielectric layer structure. The dielectric layer structure may include a plurality of first dielectric layers and a plurality of second dielectric layers that are alternately stacked. The plurality of first dielectric layers may include a ferroelectric material, and the plurality of second dielectric layers may include an anti-ferroelectric material. The distribution proportion of internal defect dipoles gradually may vary in a thickness direction of the dielectric layer structure.

公开(公告)号：US20230320075A1

公开(公告)日：2023-10-05

申请号：US17979187

申请日：2022-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin PARK ,  Hanjin LIM ,  Hyungsuk JUNG

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033

Abstract: An integrated circuit (IC) device includes a lower electrode on a substrate. The lower electrode includes a metal-containing film including a first metal. A dielectric film covers the lower electrode. An upper electrode faces the lower electrode with the dielectric film therebetween. The lower electrode includes a main lower electrode layer including no metal dopant of a different type from the first metal. The main lower electrode layer is apart from the dielectric film. An interfacial lower electrode layer is in contact with the dielectric film and includes a first metal dopant and a second metal dopant. The first metal dopant is in a first valence state and includes a second metal, which is different from the first metal. The second metal dopant is in a second valence state, which is less than the first valence state, and includes a third metal, which is different from the first and second metals.

公开(公告)号：US20230262959A1

公开(公告)日：2023-08-17

申请号：US18076599

申请日：2022-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin PARK ,  Hanjin LIM

IPC: H01L29/94

CPC classification number: H01L27/10814 ,  H01L27/10885 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876

Abstract: A semiconductor memory device includes a substrate, and a capacitor structure on the substrate and including a lower electrode, a capacitor dielectric layer, and an upper electrode, wherein the capacitor dielectric layer includes a lower interface layer on the lower electrode and doped with impurities of a first conductive type, an upper interface layer beneath the upper electrode and doped with impurities of a second conductive type other than the first conductive type, and a dielectric structure between the lower interface layer and the upper interface layer.

公开(公告)号：US20230255013A1

公开(公告)日：2023-08-10

申请号：US17878201

申请日：2022-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beomjong KIM ,  Hanjin LIM

IPC: H01L27/108 ,  H01L27/08 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L27/10852 ,  H01L27/0805 ,  H01L27/10894 ,  H01L28/90 ,  H01L21/76897 ,  H01L21/31111

Abstract: A semiconductor device includes first electrodes on a substrate and spaced apart from each other in a horizontal direction substantially parallel to an upper surface of the substrate, first support patterns contacting sidewalls of the first electrodes, a dielectric layer on surfaces of the first electrodes and the first support patterns, and a second electrode on the dielectric layer. The first support patterns are arranged in a first direction substantially parallel to the upper surface of the substrate, the first support patterns contact sidewalls of central portions of the first electrodes in a second direction substantially parallel to the upper surface of the substrate and substantially orthogonal to the first direction, and the first support patterns are not in contact with sidewalls of edge portions of the first electrodes in the second direction.

公开(公告)号：US20230163162A1

公开(公告)日：2023-05-25

申请号：US17941688

申请日：2022-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Intak JEON ,  Jiye BAEK ,  Hanjin LIM

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/91

Abstract: A semiconductor device of the disclosure may include a substrate, a gate structure on the substrate, a capacitor contact structure connected to the substrate, a lower electrode connected to the capacitor contact structure, a supporter supporting a sidewall of the lower electrode, an interfacial layer covering the lower electrode and including a halogen material, a capacitor insulating layer covering the interfacial layer and the supporter, and an upper electrode covering the capacitor insulating layer. The interfacial layer may include a first surface contacting the lower electrode, and a second surface contacting the capacitor insulating layer. The halogen material of the interfacial layer may be closer to the first surface than to the second surface.

公开(公告)号：US20230062485A1

公开(公告)日：2023-03-02

申请号：US17683506

申请日：2022-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanjin LIM ,  Younsoo KIM ,  Sunmin MOON ,  Jungmin PARK ,  Hyungsuk JUNG

IPC: H01J37/32 ,  H01L21/67

Abstract: A batch-type apparatus for atomic layer etching (ALE), which is capable of ALE-processing several wafers at the same time, and an ALE method and a semiconductor device manufacturing method based on the batch-type apparatus, are provided. The batch-type apparatus for ALE includes a wafer stacking container in which a plurality of wafers are arranged in a vertical direction, an inner tube extending in the vertical direction, a plurality of nozzles arranged in a first outer portion in the inner tube in a horizontal direction, and a heater surrounding the inner tube and configured to adjust a temperature in the inner tube, wherein gas injection holes are formed corresponding to a height of the plurality of wafers in each of the plurality of nozzles, and a gas outlet is formed in a second outer portion in the inner tube, opposite to the first outer portion.

公开(公告)号：US20220115496A1

公开(公告)日：2022-04-14

申请号：US17315947

申请日：2021-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin PARK ,  Hanjin LIM ,  Haeryong KIM ,  Younglim PARK ,  Cheoljin CHO

IPC: H01L49/02

Abstract: An integrated circuit device including a first electrode layer including a first metal and having a first thermal expansion coefficient; a dielectric layer on the first electrode layer, the dielectric layer including a second metal oxide including a second metal that is different from the first metal, and having a second thermal expansion coefficient that is less than the first thermal expansion coefficient; and a first stress buffer layer between the first electrode layer and the dielectric layer, the first stress buffer layer including a first metal oxide including the first metal, and being formed due to thermal stress of the first electrode layer and thermal stress of the dielectric layer.