公开(公告)号：US20230024307A1

公开(公告)日：2023-01-26

申请号：US17590087

申请日：2022-02-01

Applicant: Samsung Electronics Co., Ltd

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Jongman PARK ,  Dongsoo WOO

IPC: H01L27/11507

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a substrate; a transistor disposed above the substrate, the transistor having a channel region defining an inner space; and a capacitor passing through the transistor in a vertical direction in the inner space.

公开(公告)号：US20220367479A1

公开(公告)日：2022-11-17

申请号：US17716215

申请日：2022-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Dongsoo WOO ,  Sungwon YOO

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/792

Abstract: A semiconductor memory device includes a semiconductor substrate a gate structure extending in a vertical direction on the semiconductor device, a plurality of charge trap layers spaced apart from each other in the vertical direction and each having a horizontal cross-section with a first ring shape surrounding the gate structure, a plurality of semiconductor patterns spaced apart from each other in the vertical direction and each having a horizontal cross-section with a second ring shape surrounding the plurality of charge trap layers, a source region and a source line at one end of each of the plurality of semiconductor patterns in a horizontal direction, and a drain region and a drain line at an other end of each of the plurality of semiconductor patterns in the horizontal direction. The gate structure may include a gate insulation layer and a gate electrode layer.

公开(公告)号：US20220352170A1

公开(公告)日：2022-11-03

申请号：US17725069

申请日：2022-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Ilgweon KIM ,  Hyeoungwon SEO ,  Sungwon YOO ,  Jaeho HONG

IPC: H01L27/108

Abstract: A semiconductor memory device includes a word line extending in a vertical direction, a semiconductor pattern having a ring-shaped horizontal cross-section that extends around the word line, a bit line disposed at a first end of the semiconductor pattern, and a capacitor structure disposed at second end of the semiconductor pattern. The capacitor structure includes a lower electrode layer electrically connected to the second end of the semiconductor pattern, having a ring-shaped horizontal cross-section, and including a connector extending in the vertical direction. A first segment extends in a horizontal direction from an upper end of the connector, and a second segment extends in the horizontal direction from a lower end of the connector. An upper electrode layer surrounded by the lower electrode layer, extends in the vertical direction, and a capacitor dielectric layer is between the lower electrode layer and the upper electrode layer.

公开(公告)号：US20220216239A1

公开(公告)日：2022-07-07

申请号：US17503713

申请日：2021-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwon YOO ,  Yongseok KIM ,  Ilgweon KIM ,  Hyuncheol KIM ,  Hyeoungwon SEO ,  Kyunghwan LEE ,  Jaeho HONG

IPC: H01L27/12 ,  H01L27/13 ,  H01L25/065 ,  H01L25/18 ,  H01L21/84

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a data storage layer including data storage devices, an interconnection layer disposed on the data storage layer, and a selection element layer provided between the data storage layer and the interconnection layer. The interconnection layer may include bit lines extending in a first direction. The selection element layer may include a cell transistor connected between one of the data storage devices and one of the bit lines, and the cell transistor may include an active pattern and a word line, which crosses the active pattern and is extended in a second direction crossing the first direction.

公开(公告)号：US20250113590A1

公开(公告)日：2025-04-03

申请号：US18976522

申请日：2024-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Huijung KIM ,  Satoru YAMADA ,  Sungwon YOO ,  Kyunghwan LEE ,  Jaeho HONG

IPC: H01L29/74 ,  H10B12/10

Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

公开(公告)号：US20240421613A1

公开(公告)日：2024-12-19

申请号：US18742518

申请日：2024-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE

IPC: H02J7/00

Abstract: An electronic device according to an embodiment may include: a battery, load, charging circuitry, and control circuitry. The charging circuitry may include a plurality of switches and be configured to, in a PPS mode, receive power adjusted in each specified charging period according to a charge amount of the battery from an external electronic device, convert a voltage of the received power based on a specified voltage conversion ratio using the plurality of switches, and supply the voltage-converted power to the battery and the load. The control circuitry may be configured to: control a gate voltage of at least one specified switch of the plurality of switches, based on a voltage of the battery being higher than a maximum allowed charging voltage or a current of the battery being higher than a maximum allowed charging current during the PPS mode.

公开(公告)号：US20240322048A1

公开(公告)日：2024-09-26

申请号：US18606081

申请日：2024-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Jeonil LEE ,  Minhee CHO ,  Daweon HA

IPC: H01L29/792 ,  H10B12/00

CPC classification number: H01L29/7926 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488

Abstract: Provided is an integrated circuit device including a source line extending in a first horizontal direction on a substrate, a channel layer extending in a vertical direction, disposed on the source line, and having a first sidewall and a second sidewall, a trapping layer on the first sidewall of the channel layer and including an oxide semiconductor, a word line on at least one sidewall of the trapping layer and extending in a second horizontal direction crossing the first horizontal direction, a gate insulation layer between the at least one sidewall of the trapping layer and the word line, and a bit line electrically connected to the channel layer and extending in the first horizontal direction, wherein the channel layer has a first bandgap energy, and the trapping layer has a second bandgap energy that is greater than the first bandgap energy.

公开(公告)号：US20240191932A1

公开(公告)日：2024-06-13

申请号：US18583013

申请日：2024-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan LEE ,  Youngdeog KOH ,  Jihwan CHUN ,  Heecheol KANG ,  Kwangjoo KIM ,  Jinju KIM ,  Minkyung LEE

IPC: F25D23/00 ,  B23K26/359 ,  B41M5/00 ,  C23F1/36 ,  C25D11/04

CPC classification number: F25D23/00 ,  B41M5/0058 ,  C23F1/36 ,  C25D11/04 ,  B23K26/359 ,  F25D2323/06

Abstract: A manufacturing method of an aluminum exterior panel including preparing an aluminum material; machining to shape an edge of the aluminum material; implementing a fine multilayered pattern on a surface of the processed aluminum material; forming of forming fine corrugations on the surface of the aluminum material on which the fine multilayered pattern is implemented; anodizing to form pores on the surface of the aluminum material on which the fine corrugations are formed; digital printing of implementing a color and an image on the aluminum material on which the pores are formed; and sealing to close the pores.

公开(公告)号：US20230389290A1

公开(公告)日：2023-11-30

申请号：US18200135

申请日：2023-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil LEE ,  Kyunghwan LEE ,  Min Hee CHO

IPC: H10B12/00 ,  H10B53/10 ,  H10B53/30 ,  H01L29/08

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/485 ,  H10B53/10 ,  H10B53/30 ,  H01L29/0847

Abstract: A semiconductor device includes a first single crystal semiconductor pattern including a first source/drain region, a second source/drain region, and a first vertical channel region between the first source/drain region and the second source/drain region, the second source/drain region being at a higher level than the first source/drain region; a first gate electrode facing a first side surface of the first single crystal semiconductor pattern; a first gate dielectric layer, the first gate dielectric layer including a portion between the first single crystal semiconductor pattern and the first gate electrode; and a complementary structure in contact with a second side surface of the first single crystal semiconductor pattern, wherein the complementary structure includes an oxide semiconductor layer.

公开(公告)号：US20230380176A1

公开(公告)日：2023-11-23

申请号：US18102349

申请日：2023-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daewon HA ,  Kyunghwan LEE ,  Youngnam Hwang

IPC: H10B51/30 ,  H10B51/40

CPC classification number: H10B51/30 ,  H10B51/40

Abstract: A semiconductor device includes a cell region including a plurality of memory cells, and a peripheral circuit region controlling the plurality of memory cells. Each of the plurality of memory cells includes a first active region and a second active region adjacent to each other, a first channel layer and a second channel layer extending in the first direction, connected to the first active region and the second active region, and separated from each other in the third direction, a first ferroelectric layer and a first gate electrode layer sequentially provided on the first channel layer, and a second ferroelectric layer and a second gate electrode layer sequentially provided on the second channel layer. The first gate electrode layer and the second gate electrode layer are separated from each other in the third direction.