公开(公告)号：US09293093B2

公开(公告)日：2016-03-22

申请号：US14231001

申请日：2014-03-31

Applicant: Samsung Display Co., LTD.

Inventor： Jong-Hee Kim ,  Yeong-Keun Kwon ,  Ji-Sun Kim ,  Jae-Keun Lim ,  Chong-Chul Chai

IPC: G09G3/36

CPC classification number: G09G3/3611 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/08

Abstract: A gate driver circuit includes an N-th stage (‘N’ is a natural number) The N-th stage (‘N’ is a natural number) includes a pull-up part configured to output an N-th gate signal using a first clock signal in response to a node signal of the control node, a carry part configured to output an N-th carry signal using the first clock signal in response to the node signal of the control node, an first output part connected to an n-th gate line and configured to output an n-th gate signal using the N-th gate signal in response to a second clock signal having a period shorter than the first clock signal (‘n’ is a natural number), and a second output part connected to an (n+1)-th gate line and configured to output an (n+1)-th gate signal using the N-th gate signal in response to an second inversion clock signal having a phase opposite to the second clock signal.

Abstract translation: 栅极驱动器电路包括第N级（“N”是自然数）第N级（“N”是自然数）包括被配置为使用第n级输出第N门信号的上拉部分 响应于所述控制节点的节点信号的第一时钟信号，被配置为响应于所述控制节点的节点信号而使用所述第一时钟信号输出第N进位信号的进位部分，连接到所述控制节点的第一输出部分 并且被配置为响应于具有比第一时钟信号（'n'是自然数）短的周期的第二时钟信号，使用第N个门信号输出第n个门信号，第二 输出部分连接到第（n + 1）栅极线，并被配置为响应于具有与第二栅极相反相位的第二反相时钟信号，使用第N栅极信号输出第（n + 1）栅极信号 时钟信号。

公开(公告)号：US09091892B2

公开(公告)日：2015-07-28

申请号：US14208262

申请日：2014-03-13

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sung Man Kim ,  Yeong-Keun Kwon ,  Duk-Sung Kim ,  Min-Chul Song ,  Eu Gene Lee ,  Soo Jung Chae

IPC: G02F1/1345 ,  G02F1/1341

CPC classification number: G02F1/1345 ,  G02F1/1341 ,  G02F1/13452 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/1362

Abstract: A liquid crystal display includes a first substrate, gate lines and data lines disposed on a display area of the first substrate, a common voltage line disposed on a peripheral area of the first substrate, a common voltage transmission unit extending from the common voltage line, an organic layer disposed on the common voltage transmission unit and the common voltage line, a connecting member disposed on the organic layer disposed on the peripheral area, a first insulating layer disposed on the pixel electrode and the connecting member, a common electrode disposed on the first insulating layer, and a short point connecting the connecting member and the common electrode to each other. The common electrode and the first insulating layer include a plurality of cutouts in the peripheral region and display region of the first substrate which have substantially a same plane shape as each other.

Abstract translation: 液晶显示器包括第一基板，设置在第一基板的显示区域上的栅极线和数据线，设置在第一基板的周边区域上的公共电压线，从公共电压线延伸的公共电压传输单元， 设置在公共电压传输单元和公共电压线上的有机层，设置在设置在周边区域上的有机层上的连接构件，设置在像素电极和连接构件上的第一绝缘层， 第一绝缘层和将连接构件和公共电极彼此连接的短路点。 公共电极和第一绝缘层包括在周边区域中的多个切口和第一基板的显示区域，其彼此具有大致相同的平面形状。

公开(公告)号：US20150042638A1

公开(公告)日：2015-02-12

申请号：US14456976

申请日：2014-08-11

Applicant: SAMSUNG DISPLAY CO., LTD. ,  Industry-University Cooperation Foundation Hanyang-University

Inventor： Oh-Kyong Kwon ,  Yeong-Keun Kwon ,  Jong-Hee Kim ,  Ji-Sun Kim ,  Jae-Keun Lim ,  Chong-Chul Chai

IPC: G09G3/36

CPC classification number: G09G3/3225 ,  G09G3/3266 ,  G09G2310/0264 ,  G09G2310/0289 ,  G09G2310/08 ,  G11C19/28

Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Abstract translation: 舞台电路包括第一驱动器，第二驱动器，第一输出单元，第二输出单元和控制器。 第一驱动器根据第一电源，第三电源，开始信号或前一级输入到第一输入端的进位信号来控制第一和第二节点的电压，以及提供给第二输入端的时钟信号 终奌站。 第二驱动器根据第一电源，第三电源，第一输入端和第一和第二节点的电压来控制第三和第四节点的电压。 第一输出单元根据第一电源，第二输入端和第三和第四节点的电压将输入信号输出到第一输出端。 第二输出单元根据第二电源，第二输入端和第三和第四节点的电压向第二输出端输出扫描信号。 控制器电耦合到第一输出端子和第二驱动器。

公开(公告)号：US20150042383A1

公开(公告)日：2015-02-12

申请号：US14456995

申请日：2014-08-11

Applicant: Samsung Display Co., Ltd. ,  Industry-University Cooperation Foundation Hanyang-University

Inventor： Oh-Kyong Kwon ,  Yeong-Keun Kwon ,  Jong-Hee Kim ,  Ji-Sun Kim ,  Jae-Keun Lim ,  Chong-Chul Chai

IPC: G09G3/14 ,  H03K17/687

CPC classification number: H03K17/687 ,  G09G3/3266 ,  G09G2310/0286 ,  G09G2310/06 ,  G11C19/184 ,  G11C19/28

Abstract: A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.

Abstract translation: 舞台电路包括第一驱动器，第二驱动器，第一输出单元和第二输出单元。 第一驱动器根据第一电源，提供给第一输入端的前一级的起始信号或进位信号，提供给第二输入端的第一时钟信号和第二驱动器控制第一和第二节点的电压， 提供给第三输入端的时钟信号。 第二驱动器根据第一电源控制第三节点的电压，提供给第一输入端的先前级的起始信号或进位信号，提供给第四输入端的下一级的进位信号， 和第二节点的电压。

公开(公告)号：US08816728B2

公开(公告)日：2014-08-26

申请号：US14057354

申请日：2013-10-18

Applicant: Samsung Display Co., Ltd.

Inventor： Soo-Wan Yoon ,  Yeong-Keun Kwon ,  Ji-Sun Kim ,  Young-Soo Yoon ,  Chong-Chui Chai

IPC: H03K3/00

CPC classification number: H03K3/012 ,  G09G3/3674 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/184 ,  G11C19/28

Abstract: A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.

Abstract translation: 栅极驱动电路包括上拉控制部分，上拉部分，携带部分，第一下拉部分和第二下拉部分。 上拉控制部分将来自前一级的进位信号应用于第一节点。 上拉部分基于时钟信号输出第N个栅极输出信号。 进位部分响应于施加到第一节点的信号，基于时钟信号输出第N个进位信号。 第一下拉部分包括彼此串联连接的多个晶体管。 第一下拉部分响应于下一级的进位信号将第一节点处的信号拉低至第二截止电压。 第二下拉部分响应于下一级的进位信号将第N栅极输出信号拉低至第一关断电压。

公开(公告)号：US20140218347A1

公开(公告)日：2014-08-07

申请号：US14167868

申请日：2014-01-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： CHEOL-GON LEE ,  Chong Chul Chai ,  Joon-Chul Goh ,  Yeong-Keun Kwon ,  Jong Hee Kim

IPC: G02F1/1362 ,  G09G3/36

CPC classification number: G02F1/136286 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2320/028

Abstract: In a liquid crystal display one pixel is divided into two subpixels, the two subpixels are connected to two subdata lines extending from one data line, and a desired data voltage is applied by using a data driving switching element connected to the subdata line, thereby reducing the number of data lines needed to reduce the cost of the driver and preventing a lack of space to mount the data driver while dividing one pixel into two subpixels and differently applying voltages of the two subpixels.

Abstract translation: 在液晶显示器中，一个像素被分成两个子像素，两个子像素连接到从一个数据线延伸的两个子数据线，并且通过使用连接到子数据线的数据驱动开关元件来施加期望的数据电压，从而减少 减少驱动器成本所需的数据线数量，并且防止在将一个像素分成两个子像素并且不同地施加两个子像素的电压时安装数据驱动器的空间不足。

公开(公告)号：US20140043066A1

公开(公告)日：2014-02-13

申请号：US14057354

申请日：2013-10-18

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Soo-Wan Yoon ,  Yeong-Keun Kwon ,  Ji-Sun Kim ,  Young-Soo Yoon ,  Chong-Chul Chai

IPC: H03K3/012

CPC classification number: H03K3/012 ,  G09G3/3674 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/184 ,  G11C19/28

Abstract: A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.

Abstract translation: 栅极驱动电路包括上拉控制部分，上拉部分，携带部分，第一下拉部分和第二下拉部分。 上拉控制部分将来自前一级的进位信号应用于第一节点。 上拉部分基于时钟信号输出第N个栅极输出信号。 进位部分响应于施加到第一节点的信号，基于时钟信号输出第N个进位信号。 第一下拉部分包括彼此串联连接的多个晶体管。 第一下拉部分响应于下一级的进位信号将第一节点处的信号拉低至第二截止电压。 第二下拉部分响应于下一级的进位信号将第N栅极输出信号拉低至第一关断电压。