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21.发明授权公开(公告)号：US09584096B2
公开(公告)日：2017-02-28
申请号：US14704291
申请日：2015-05-05
Applicant: Skyworks Solutions, Inc.
Inventor： Joshua Haeseok Cho , Yunyoung Choi , Bipul Agarwal
CPC classification number: H03H11/245 , H03H11/16 , H04L25/03828
Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a digital step attenuator (DSA) includes a plurality of DSA stages arranged in a cascade between an input terminal and an output terminal. Each of the DSA stages can be operated in an attenuation mode or in a bypass mode. The DSA further includes an attenuation control circuit, which can be used to control the modes of operation of the DSA stages. The attenuation control circuit can be used to operate the DSA over a plurality of attenuation steps, which can be digitally selectable. To provide low phase shift across the range of attenuation steps, a DSA stage can include one or more phase compensation capacitors used to provide low phase shift and to compensate for a phase difference between the DSA stage operating in the bypass mode and in the attenuation mode.
Abstract translation: 本文提供了用于数字步进衰减器的装置和方法。 在某些配置中，数字步进衰减器（DSA）包括在输入端子和输出端子之间级联布置的多个DSA级。 每个DSA级可以在衰减模式或旁路模式下工作。 DSA还包括一个衰减控制电路，可用于控制DSA级的工作模式。 衰减控制电路可以用于在多个衰减步骤中操作DSA，其可以是数字可选择的。 为了在衰减步骤的范围内提供低相移，DSA级可以包括一个或多个相位补偿电容器，用于提供低相移并补偿在旁路模式和衰减模式下工作的DSA级之间的相位差 。
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公开(公告)号：US20240421788A1
公开(公告)日：2024-12-19
申请号：US18752465
申请日：2024-06-24
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung Lee , Johannes Jacobus Emile Maria Hageraats , Yan Yan , Bumkyum Kim , Aravind Kumar Padyana , Joshua Haeseok Cho , Rimal Deep Singh , Bipul Agarwal
Abstract: Disclosed herein are signal amplifiers that include a plurality of switchable amplifier architectures so that particular gain modes can use dedicated amplifier architectures to provide desired characteristics for those gain modes, such as low noise figure or high linearity. The disclosed signal amplifier architectures provide tailored impedances using a degeneration block or matrix without using switches in the degeneration switching block. The disclosed signal amplifier architectures provide a plurality of gain modes where different gain modes use different paths through the amplifier architecture. Switches that are used to select the path through the amplifier architecture also provide targeted impedances in a degeneration block or matrix. The switches that select the gain path are provided in the amplifier architecture and are thus not needed or used in the degeneration block, thereby reducing the size of the package for the amplifier architecture.
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23.发明授权公开(公告)号：US11527997B2
公开(公告)日：2022-12-13
申请号：US17021976
申请日：2020-09-15
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung Lee , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
IPC: H03F1/02 , H03F3/19 , H03F1/56 , H03G3/30 , H03F1/22 , H03F1/32 , H03F3/193 , H03F3/72 , H03G1/00 , H03G5/28 , H04B1/3827
Abstract: Disclosed herein are signal amplifiers having a plurality of amplifier cores. Individual amplifier cores can be designed to enhance particular advantages while reducing other disadvantages. The signal amplifier can then switch between amplifier cores in a particular gain mode to achieve desired performance characteristics (e.g., improving noise figure or linearity). Examples of signal amplifiers disclosed herein include amplifier architectures with a low noise figure amplifier core that reduces the noise figure and a linearity boost amplifier core that increases linearity. The disclosed signal amplifiers can switch between a first active core and a second active core for a single or particular gain mode to achieve desired signal characteristics during different time periods.
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公开(公告)号：US10797668B2
公开(公告)日：2020-10-06
申请号：US16504252
申请日：2019-07-06
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung Lee , Rimal Deep Singh , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Bipul Agarwal , Aravind Kumar Padyana
Abstract: Described herein are variable gain amplifiers and multiplexers that embed programmable attenuators into switchable paths to provide variable gain for individual amplifier inputs. The variable gain for an individual input is provided using a amplification stage that is common for each input of the amplifier. A variable attenuation is provided for individual inputs through a combination of a band selection switch and an attenuation selection branch. The attenuation can be tailored for individual inputs and can depend on a gain mode of the amplifier.
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公开(公告)号：US20200007102A1
公开(公告)日：2020-01-02
申请号：US16504252
申请日：2019-07-06
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung LEE , Rimal Deep Singh , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Bipul Agarwal , Aravind Kumar Padyana
Abstract: Described herein are variable gain amplifiers and multiplexers that embed programmable attenuators into switchable paths to provide variable gain for individual amplifier inputs. The variable gain for an individual input is provided using a amplification stage that is common for each input of the amplifier. A variable attenuation is provided for individual inputs through a combination of a band selection switch and an attenuation selection branch. The attenuation can be tailored for individual inputs and can depend on a gain mode of the amplifier.
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Patent Agency Ranking
公开(公告)号：US10389305B2
公开(公告)日：2019-08-20
申请号：US15849434
申请日：2017-12-20
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung Lee , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
IPC: H03F3/72 , H03F1/02 , H03F3/19 , H03F1/56 , H03G3/30 , H03G1/00 , H03G5/28 , H03F1/22 , H03F1/32 , H03F3/193 , H04B1/3827
Abstract: Disclosed herein are signal amplifiers having a plurality of amplifier cores. Individual amplifier cores can be designed for particular gain modes to enhance particular advantages while reducing other disadvantages. The signal amplifier can then switch between amplifier cores when switching gain modes to achieve desired performance characteristics (e.g., improving noise figure or linearity). Examples of signal amplifiers disclosed herein include amplifier architectures with a high gain amplifier core that reduces the noise figure and a linearity boost amplifier core that increases linearity (e.g., for lower gain modes). The disclosed signal amplifiers can also have switchable reference biases to provide targeted bias current matching. The disclosed signal amplifiers can also include degeneration switching blocks for individual amplifier cores to improve signal linearity.
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公开(公告)号：US20190207639A1
公开(公告)日：2019-07-04
申请号：US16351446
申请日：2019-03-12
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Johannes Jacobus Emile Maria Hageraats , Junhyung Lee , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
Abstract: Described herein are variable gain amplifiers that selectively provide variable or tailored impedances at a degeneration block and/or feedback block depending at least in part on a gain mode of the variable gain amplifier. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality. The degeneration block can be selectively isolated from a reference potential node to improve performance.
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公开(公告)号：US10056880B2
公开(公告)日：2018-08-21
申请号：US15678967
申请日：2017-08-16
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Joshua Haeseok Cho , Yunyoung Choi , Bipul Agarwal
CPC classification number: H03H11/245 , H03H11/24 , H04M1/0277
Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.
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29.发明申请公开(公告)号：US20150326205A1
公开(公告)日：2015-11-12
申请号：US14704291
申请日：2015-05-05
Applicant: Skyworks Solutions, Inc.
Inventor： Joshua Haeseok Cho , Yunyoung Choi , Bipul Agarwal
CPC classification number: H03H11/245 , H03H11/16 , H04L25/03828
Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a digital step attenuator (DSA) includes a plurality of DSA stages arranged in a cascade between an input terminal and an output terminal. Each of the DSA stages can be operated in an attenuation mode or in a bypass mode. The DSA further includes an attenuation control circuit, which can be used to control the modes of operation of the DSA stages. The attenuation control circuit can be used to operate the DSA over a plurality of attenuation steps, which can be digitally selectable. To provide low phase shift across the range of attenuation steps, a DSA stage can include one or more phase compensation capacitors used to provide low phase shift and to compensate for a phase difference between the DSA stage operating in the bypass mode and in the attenuation mode.
Abstract translation: 本文提供了用于数字步进衰减器的装置和方法。 在某些配置中，数字步进衰减器（DSA）包括在输入端子和输出端子之间级联布置的多个DSA级。 每个DSA级可以在衰减模式或旁路模式下工作。 DSA还包括一个衰减控制电路，可用于控制DSA级的工作模式。 衰减控制电路可以用于在多个衰减步骤中操作DSA，其可以是数字可选择的。 为了在衰减步骤的范围内提供低相移，DSA级可以包括一个或多个相位补偿电容器，用于提供低相移并补偿在旁路模式和衰减模式下工作的DSA级之间的相位差 。
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公开(公告)号：US20220247441A1
公开(公告)日：2022-08-04
申请号：US17649904
申请日：2022-02-03
Applicant: Skyworks Solutions, Inc.
Inventor： Joshua Haeseok Cho , Stephane Richard Marie Wloczysiak , Thomas Obkircher , Junhyung Lee , Rimal Deep Singh , Bipul Agarwal
Abstract: Radio frequency front end modules implementing coexisting time division duplexing and frequency division duplexing are provided. In one aspect, a front end system includes a time-division duplexing transmit terminal, a time-division duplexing receive terminal, a frequency division duplexing terminal, and an antenna terminal. The front end system further includes first, second, and third switches configured to selectively connect the terminals to either a node or the antenna. The front end system also includes a controller configured to provide delays between disconnecting the terminals from the antenna and connecting the terminals to the node.
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