公开(公告)号：US20210066278A1

公开(公告)日：2021-03-04

申请号：US16863736

申请日：2020-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANHO KIM ,  KYUNGHWA YUN ,  DAESEOK BYEON

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00

Abstract: A non-volatile memory device includes a first semiconductor layer having a stair area and a cell area having a memory cell array formed therein, and a second semiconductor layer including a page buffer connected to the memory cell array. The first semiconductor layer includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.

公开(公告)号：US20210066277A1

公开(公告)日：2021-03-04

申请号：US16850493

申请日：2020-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHANHO KIM ,  JOO-YONG PARK ,  DAESEOK BYEON

IPC: H01L25/18 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11582 ,  H01L49/02 ,  H01L27/11565 ,  H01L23/00 ,  H01L27/11575

Abstract: A three-dimensional semiconductor memory device, including a first chip and a second chip stacked on the first chip may be provided. The first chip may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, and second contact plugs, and a passive device on and electrically connected to the second contact plugs. The second chip may include a second substrate including a cell array region and a contact region, which vertically overlap the second peripheral circuit region and the first peripheral circuit region of the first chip, respectively. The second chip may further include gate electrodes, and cell contact plugs disposed on the contact region of the second substrate and on end portions of the gate electrodes. The first passive device may be vertically between the gate electrodes and the second contact plugs and may include a first contact line.

公开(公告)号：US20180366199A1

公开(公告)日：2018-12-20

申请号：US16049863

申请日：2018-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHUN KWAK ,  DAESEOK BYEON ,  CHIWEON YOON

IPC: G11C16/08 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0483

Abstract: A nonvolatile memory device includes a memory cell array having a first plane and a second plane and an address decoder connected to the first plane through first string select lines and connected to the second plane through second string select line. The address decoder provides a string select signal and a string unselect signal to the first and second string select lines. The address decoder independently provides the string select signal and the string unselect signal to the first and second string select lines in each plane based on different string select line addresses corresponding to the first and second planes.

公开(公告)号：US20180068728A1

公开(公告)日：2018-03-08

申请号：US15806543

申请日：2017-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-SANG LEE ,  DONGHUN KWAK ,  DAESEOK BYEON ,  CHIWEON YOON

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26

Abstract: A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.