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    Generating a temperature-compensated write current for a magnetic memory cell
    21.
    发明授权
    Generating a temperature-compensated write current for a magnetic memory cell 有权
    为磁存储单元产生温度补偿写入电流

    公开(公告)号：US08339843B2

    公开(公告)日：2012-12-25

    申请号：US12971244

    申请日：2010-12-17

    Applicant: Romney R. Katti

    Inventor： Romney R. Katti

    IPC: G11C11/00

    CPC classification number: G11C7/04 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1697

    Abstract: This disclosure describes write current temperature compensation techniques for use in programming a data storage device that includes one or more memory cells. The techniques may include programming a programmable magnetization state of a magnetoresistive device included within a resistance network based on a signal indicative of the operating temperature of a magnetic memory cell. The techniques may further include generating a write current having a magnitude that is determined at least in part by the programmable magnetization state of the magnetoresistive device. The techniques may further include supplying the write current to the magnetic memory cell for programming a programmable magnetization state of the magnetic memory cell.

    Abstract translation: 本公开描述了用于编程包括一个或多个存储器单元的数据存储设备的写入当前温度补偿技术。 这些技术可以包括基于指示磁存储器单元的工作温度的信号来编程包括在电阻网络内的磁阻器件的可编程磁化状态。 这些技术可以进一步包括产生具有至少部分由磁阻器件的可编程磁化状态确定的幅度的写入电流。 这些技术可以进一步包括向磁性存储单元提供写入电流以编程磁性存储单元的可编程磁化状态。

    MRAM read bit with askew fixed layer
    22.
    发明申请
    MRAM read bit with askew fixed layer 失效

    公开(公告)号：US20090073755A1

    公开(公告)日：2009-03-19

    申请号：US11376433

    申请日：2006-03-15

    Applicant: Romney R. Katti

    Inventor： Romney R. Katti

    IPC: G11C11/14 ,  H01L29/82

    CPC classification number: G11C11/1673 ,  H01L43/08

    Abstract: A new read scheme is provided for an MRAM bit having a reference layer (fixed) and a storage layer (free) sandwiching a nonmagnetic spacer layer. The reference layer has a magnetization direction that is tilted with respect to an easy axis of the storage layer. By applying a magnetic field to the bit at least partially orthogonal to the easy axis, the magnetization direction of the storage layer can be partially rotated or canted without switching the logical state of the MRAM bit. The resistivity of the bit is measured (calculated based on a voltage/current relationship) in two ways: (i) with the magnetization direction of the storage layer partially rotated in a first direction and (ii) with the magnetization direction of the storage layer in its bi-stable orientation parallel to the easy axis. Those measures can then be used to compare and determine the logical state of the storage layer.

    Magnetoresistive Element with a Biasing Layer
    23.
    发明申请
    Magnetoresistive Element with a Biasing Layer 审中-公开
    具有偏置层的磁阻元件

    公开(公告)号：US20090034321A1

    公开(公告)日：2009-02-05

    申请号：US11832416

    申请日：2007-08-01

    Applicant: Romney R. Katti

    Inventor： Romney R. Katti

    IPC: G11C11/00

    CPC classification number: H01F10/3272 ,  B82Y25/00 ,  G11C11/161

    Abstract: An improved magnetoresistive element may include a pinned magnetic structure, a free magnetic structure, and a spacer layer coupled between the pinned magnetic structure and the free magnetic structure, where the free magnetic structure includes (i) a synthetic anti-ferromagnetic structure (SAF) including two or more anti-ferromagnetically coupled ferromagnetic layers, and (ii) a first biasing layer coupled to the SAF that impedes a decoupling of the two or more anti-ferromagnetically coupled ferromagnetic layers. The first biasing layer may be an anti-ferromagnetic layer, and may be weakly coupled to the SAF. The free magnetic structure may also include (i) a second biasing layer coupled to the SAF that further impedes a decoupling of the two or more anti-ferromagnetically coupled ferromagnetic layers, and/or (ii) a non-magnetic layer coupled between the first biasing layer and the SAF that controls a coupling strength between the first biasing layer and the SAF.

    Abstract translation: 改进的磁阻元件可以包括钉扎磁结构，自由磁结构和耦合在钉扎磁结构和自由磁结构之间的间隔层，其中自由磁结构包括（i）合成反铁磁结构（SAF） 包括两个或更多个反铁磁耦​​合铁磁层，以及（ii）耦合到SAF的第一偏置层，其阻止两个或更多个反铁磁耦​​合的铁磁层的去耦合。 第一偏置层可以是反铁磁性层，并且可能弱耦合到SAF。 自由磁结构还可以包括（i）耦合到SAF的第二偏置层，其进一步阻碍两个或更多个反铁磁耦​​合的铁磁层的去耦合，和/或（ii）耦合在第一 偏压层和控制第一偏压层和SAF之间的耦合强度的SAF。

    MRAM read sequence using canted bit magnetization
    24.
    发明授权
    MRAM read sequence using canted bit magnetization 有权

    公开(公告)号：US07248496B2

    公开(公告)日：2007-07-24

    申请号：US11273214

    申请日：2005-11-14

    Applicant: Romney R. Katti ,  Owen J. Hynes ,  Daniel S. Reed ,  Hassan Kaakani

    Inventor： Romney R. Katti ,  Owen J. Hynes ,  Daniel S. Reed ,  Hassan Kaakani

    IPC: G11C7/00

    CPC classification number: G11C11/16

    Abstract: A new read scheme is provided for an MRAM bit having a pinned layer (fixed) and a storage layer (free) sandwiching a nonmagnetic spacer layer. By applying a magnetic field to the bit at least partially orthogonal to the easy axis of the bit, the magnetization direction of the storage layer can be partially rotated or canted without switching the logical state of the MRAM bit. The resistivity of the bit is measured (calculated based on a voltage/current relationship) in two ways: (i) with the magnetization direction of the storage layer partially rotated in a first direction and (ii) with the magnetization direction of the storage layer in its bi-stable orientation parallel to the easy axis. Those measures can then be used to compare and determine the logical state of the storage layer. For instance, if the canted resistivity is greater than the uncanted resistivity then the magnetization directions of the pinned and storage layer are parallel, and if the canted resistivity is less than the uncanted resistivity then the magnetization directions of the pinned and storage layer are opposite.

    Bit end design for pseudo spin valve (PSV) devices
    25.
    发明授权
    Bit end design for pseudo spin valve (PSV) devices 失效
    伪自旋阀（PSV）器件的位端设计

    公开(公告)号：US07183042B2

    公开(公告)日：2007-02-27

    申请号：US10706067

    申请日：2003-11-12

    Applicant: Romney R. Katti ,  Paul S. Fechner ,  Gordon A. Shaw ,  Daniel S. Reed ,  David W. Zou

    Inventor： Romney R. Katti ,  Paul S. Fechner ,  Gordon A. Shaw ,  Daniel S. Reed ,  David W. Zou

    IPC: G03F7/20

    CPC classification number: G11C11/16

    Abstract: In a process of making a magnetoresistive memory device, a mask layout is produced by use of any suitable design tool. The mask layout is laid out in grids having a central grid forming a central section and grids forming bit end sections, and the grids of the bit end sections are rectangles. A mask is made by use of the mask layout, and the mask has stepped bit ends. The mask is used to make a magnetic storage layer having tapered bit ends, to make a magnetic sense layer having tapered bit ends, and to make a non-magnetic layer having tapered bit ends. The non-magnetic layer is between the magnetic sense layer and the magnetic storage layer.

    Abstract translation: 在制造磁阻存储器件的过程中，通过使用任何合适的设计工具来生产掩模布局。 掩模布局布置在具有形成中心部分的中心格栅和形成钻头末端部分的格栅的格栅中，钻头端部的格栅为矩形。 使用掩模布局制作掩模，并且掩模具有阶梯位。 该掩模用于制造具有锥形位端的磁存储层，以形成具有锥形位端的磁感应层，并制成具有锥形位端的非磁性层。 非磁性层位于磁感应层和磁性存储层之间。

    Bias-adjusted magnetoresistive devices for magnetic random access memory (MRAM) applications
    27.
    发明授权
    Bias-adjusted magnetoresistive devices for magnetic random access memory (MRAM) applications 失效
    用于磁随机存取存储器（MRAM）应用的偏置调整磁阻器件

    公开(公告)号：US07068531B2

    公开(公告)日：2006-06-27

    申请号：US10754935

    申请日：2004-01-10

    Applicant: Romney R. Katti

    Inventor： Romney R. Katti

    IPC: G11C11/00

    CPC classification number: G11C11/16

    Abstract: A method and apparatus are presented for shifting a hysteresis loop of a magnetoresistive device. For example, a method provides for applying a bias current to a word line of the magnetoresistive device during either a read sequence or a write sequence. The bias current is preferably configured to substantially center a hysteresis loop of the device without switching a binary state of the device.

    Abstract translation: 提出了一种用于移动磁阻器件的磁滞回线的方法和装置。 例如，一种方法提供了在读取序列或写入序列期间将偏置电流施加到磁阻器件的字线。 偏置电流优选地被配置为基本上使器件的磁滞回线居中，而不会切换器件的二进制状态。

    Pseudo tunnel junction
    28.
    发明授权
    Pseudo tunnel junction 失效
    伪隧道结

    公开(公告)号：US07023724B2

    公开(公告)日：2006-04-04

    申请号：US10754881

    申请日：2004-01-10

    Applicant: Romney R. Katti

    Inventor： Romney R. Katti

    IPC: G11C11/00

    CPC classification number: G11C11/16

    Abstract: The present invention provides for a tunneling magnetoresistive element and a method of reading a logical state of the element. An embodiment of the magnetoresistive element, for example, provides a tri-layer device having a storage layer, a sense layer and a barrier layer. The storage layer is a conducting, magnetic layer having a magnetization direction along an easy axis of the element. The storage layer is configured such that its magnetization direction will invert in response to an externally applied magnetic field of at least a first threshold strength. The binary state of the tunneling element is determinable from the magnetization direction of the storage layer. The sense layer is also a conducting, magnetic layer having a magnetization direction along the easy axis of the element. The sense layer is configured such that its magnetization direction will invert in response to an externally applied magnetic field of at least a second threshold strength. The sense layer is designed with a lower coercivity than the storage layer, thus the second threshold strength is less than the first threshold strength.

    Abstract translation: 本发明提供隧道磁阻元件和读取元件的逻辑状态的方法。 例如，磁阻元件的实施例提供了具有存储层，感测层和阻挡层的三层器件。 存储层是具有沿元件的容易轴的磁化方向的导电磁性层。 存储层被配置为使得其磁化方向响应于至少第一阈值强度的外部施加的磁场而反转。 隧道元件的二进制状态可以从存储层的磁化方向确定。 感应层也是具有沿元件容易轴的磁化方向的导电磁性层。 感测层被配置为使得其磁化方向响应于至少第二阈值强度的外部施加的磁场而反转。 感应层被设计成具有比存储层更低的矫顽力，因此第二阈值强度小于第一阈值强度。

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