公开(公告)号：US10320596B2

公开(公告)日：2019-06-11

申请号：US15721467

申请日：2017-09-29

Applicant: Raytheon Company

Inventor： Daniel Thompson ,  Harry B. Marr

IPC: H04B1/10 ,  H04B3/14 ,  H04B10/2507 ,  H04L27/12 ,  H04B7/005

Abstract: Circuit and method for modulating filter coefficients of a frequency channelizer having a filter bank include: receiving a wide spectrum input signal; modulating the filter coefficients of the filter bank to sweep a center frequency of each channel of the frequency channelizer, using a modulation scheme; and inputting frequency offset compensation caused by the modulation, and output signals of the frequency channelizer to an application processing circuit to convert the output signals to their original center frequencies.

公开(公告)号：US20190067814A1

公开(公告)日：2019-02-28

申请号：US15686630

申请日：2017-08-25

Applicant: Raytheon Company

Inventor： Daniel Thompson ,  Harry B. Marr ,  Ian Robinson ,  Jeffrey Caldwell

IPC: H01Q3/38 ,  H01Q21/22 ,  G01S13/02

Abstract: A system and method of digital beamforming for a monobit phased array radar system includes providing a plurality of monobit analog signals received by at least one antenna to at least one field programmable gate array (FPGA). A plurality of monobit SerDes transceivers within the FPGA convert the plurality of monobit analog signals into a plurality of multibit digital signals, each of the multibit digital signals being modified according to a digital signal conditioning value to calibrate, phase align, and synchronize the digital signals. A digital beam is formed by coherently combining the plurality of digital signals within the FPGA.

公开(公告)号：US10116322B1

公开(公告)日：2018-10-30

申请号：US15828566

申请日：2017-12-01

Applicant: Raytheon Company

Inventor： Ian S. Robinson ,  James Toplicar ,  Daniel Thompson

IPC: H03M1/12 ,  H03M3/00 ,  G01S7/35 ,  G01S7/292

Abstract: A system and method of converting an analog input signal to a linearized digital representation of the analog input signal. A measure of the analog input signal is compared to a threshold associated with a maximum dynamic range of a quantizer. A maximum amplitude of a random, analog dither signal is dynamically varied for perturbing quantization of the analog input signal in response to the comparison. The dynamically varied dither signal and the analog input signal are combined to obtain a dithered input signal. The quantizer converts the dithered input signal into the linearized digital representation of the analog input signal.

公开(公告)号：US20170344341A1

公开(公告)日：2017-11-30

申请号：US15167346

申请日：2016-05-27

Applicant: Raytheon Company

Inventor： Harry Bourne Marr, JR. ,  Jeffery Jay Logan ,  Daniel Thompson

IPC: G06F7/38

CPC classification number: G06F7/38 ,  G06F7/68 ,  G06F2207/481

Abstract: Rate domain numerical processing comprises receiving an input serial data stream on a single input wire in which a multi-valued number is represented as a rate of pulse events comprising pulses, null pulses or a combination thereof. The rate of pulse events in an output serial data stream is varied in accordance with an operand to perform a multi-valued arithmetic operation selected from multiplication, division, addition and subtraction or a combination thereof. The rate may be varied by scaling the rate by an operand, which may be implemented using a count and compare circuit topology. The output serial data stream is output on a single output wire. The rate domain operations, specifically multiplication and division are accomplished without the resource & power intensive binary multiplier and binary divisions circuits. The operations are implemented using simple registers, adders, accumulators, counters, comparators, and basic logic, which is far more SWaP-C efficient.

公开(公告)号：US09438233B1

公开(公告)日：2016-09-06

申请号：US14839997

申请日：2015-08-30

Applicant: Raytheon Company

Inventor： Harry B. Marr ,  Kenneth E. Prager ,  Julia L. Karl ,  Daniel Thompson

IPC: H03K19/20 ,  H03K19/094 ,  H03K19/00 ,  H03K19/08

CPC classification number: H03K19/0013 ,  H03K19/0806

Abstract: A low-power digital logic architecture exhibits the same logic and voltage level behavior as standard digital logic. A logic switch and a pair of unidirectional switches are used to control the direction of charge flow in a switched-inductor capacitor (SLC) circuit, allowing the inductor to pull charge back-and-forth from one side of the load capacitor to the other to both switch the logical state at the top of the capacitor and to recycle and store the charge in the capacitor itself.

Abstract translation: 低功率数字逻辑架构具有与标准数字逻辑相同的逻辑和电压电平特性。 逻辑开关和一对单向开关用于控制开关电感电容器（SLC）电路中的电荷流动方向，允许电感器从负载电容器的一侧向前拉动负载到另一侧 两者都切换电容器顶部的逻辑状态，并将电荷循环并存储在电容器本身中。

公开(公告)号：US20150365185A1

公开(公告)日：2015-12-17

申请号：US14305685

申请日：2014-06-16

Applicant: RAYTHEON COMPANY

Inventor： Daniel Thompson ,  Harry B. Marr ,  Nnaemeka Okafor ,  Chris McLean ,  Aaron Romulo ,  Edwin Molina

IPC: H04J3/16 ,  H04J3/02

CPC classification number: H04L27/00 ,  H04B1/001 ,  H04B1/0035 ,  H04J3/02 ,  H04J3/1694 ,  H04L27/2652 ,  H04L27/2657

Abstract: Embodiments are directed to a channelizer architecture configured to provide fully configurable frequency spectrum shaping by: establishing a plurality of parameters of the architecture, receiving an input signal, processing, by the architecture, the input signal in accordance with the plurality of parameters to obtain an output signal, analyzing the output signal to detect an object, and modifying the plurality of parameters to account for at least one dynamic condition associated with the object.

Abstract translation: 实施例涉及一种被配置为通过以下方式提供完全可配置的频谱整形的信道器架构：通过以下方式提供架构的多个参数，接收输入信号，根据该结构处理输入信号，以获得 输出信号，分析输出信号以检测对象，以及修改多个参数以解决与对象相关联的至少一个动态条件。

公开(公告)号：US20150363359A1

公开(公告)日：2015-12-17

申请号：US14320839

申请日：2014-07-01

Applicant: Raytheon Company

Inventor： Harry B. Marr ,  Daniel Thompson

IPC: G06F17/14 ,  H03H17/02

CPC classification number: G06F17/142 ,  H03H17/0213 ,  H03H17/0248 ,  H04B1/001

Abstract: A butterfly channelizer includes at least two stages. Each stage includes at least one dual-channel module configured to convert an input time domain signal into a second time domain signal of lower bandwidth. At least one clock is configured to generate a clock signal that drives the at least two stages. A first stage has a first number of dual-channel modules and a second stage following the first stage has a second number of dual-channel modules greater than the first number.

Abstract translation: 蝴蝶渠道化器至少包括两个阶段。 每个级包括至少一个双通道模块，其被配置为将输入时域信号转换为较低带宽的第二时域信号。 至少一个时钟被配置为产生驱动至少两个级的时钟信号。 第一级具有第一数量的双通道模块，并且在第一级之后的第二级具有大于第一数量的第二数量的双通道模块。

公开(公告)号：US20140362774A1

公开(公告)日：2014-12-11

申请号：US13910731

申请日：2013-06-05

Applicant: Raytheon Company

Inventor： Harry B. Marr ,  Daniel Thompson ,  Julia Karl

IPC: H04K3/00

CPC classification number: H04K3/42 ,  G06F1/022 ,  H04K3/00 ,  H04K3/44

Abstract: Embodiments of a system and method for providing efficient wideband inverse channelization for direct digital synthesizer based jamming techniques are generally described herein. In some embodiments, metadata associated with a technique for generating a waveform, such as frequency, phase and amplitude parameters, is received. Data select signals and data input are generated based on the received metadata. In-phase and quadrature signals are produced at an output of a first de-multiplexer and a second de-multiplexer, respectively, based on the data select signals and the data input. Frequency modulated signals generated by direct digital synthesizers may be combined in a channel using a separate, distinct channel combiner.

Abstract translation: 本文通常描述用于为基于直接数字合成器的干扰技术提供有效的宽带反向信道化的系统和方法的实施例。 在一些实施例中，接收与用于生成波形的技术（例如频率，相位和幅度参数）相关联的元数据。 基于接收的元数据生成数据选择信号和数据输入。 基于数据选择信号和数据输入，分别在第一解复用器和第二解复用器的输出端产生同相和正交信号。 由直接数字合成器产生的频率调制信号可以使用单独的，不同的信道组合器在信道中组合。

公开(公告)号：US11063616B2

公开(公告)日：2021-07-13

申请号：US16043684

申请日：2018-07-24

Applicant: RAYTHEON COMPANY

Inventor： Alexander Scott ,  Daniel Thompson ,  Harry B. Marr

IPC: H04B1/00 ,  G01S7/288 ,  G01S13/04 ,  H04B7/08 ,  G01S7/295

Abstract: An RF detection system includes a signal routing processor and a dynamically reconfigurable channelizer. The signal routing processor selects an operating mode of the RF detection system among a plurality of different operating mode. The dynamically reconfigurable channelizer invokes the selected operating mode in response to a routing control signal output by the signal routing processor. The dynamically reconfigurable channelizer includes a plurality of signal processing resources and a crossbar switching circuit. The crossbar switching circuit includes a signal input to receive an input signal and a signal output to output a final processed signal indicating a detected object. The crossbar switching circuit selectively establishes a plurality of different signal routing paths that connect the plurality of signal processing resources to the signal input and signal output.

公开(公告)号：US10819377B1

公开(公告)日：2020-10-27

申请号：US16403442

申请日：2019-05-03

Applicant: RAYTHEON COMPANY

Inventor： Harry B. Marr ,  Daniel Thompson ,  Aleksandr S. Radunsky

IPC: H04B1/04 ,  H04B10/516 ,  H04B1/03

Abstract: A transmitter. In some embodiments, the transmitter has an electrical input and an optical output. The transmitter may include a light source; an optical amplitude modulator having an optical input connected to the light source, a modulation input connected to the electrical input, and an output; and a first gated optical comparator, having a sampling clock input, an analog input connected to the output of the optical amplitude modulator, and an output. The first gated optical comparator may be configured to generate, for each cycle of an optical sampling clock signal received at the sampling clock input, a one-bit digital representation of an analog optical signal received at the analog input.