公开(公告)号：US20130126960A1

公开(公告)日：2013-05-23

申请号：US13740045

申请日：2013-01-11

Applicant: Renesas Electronics Corporation

Inventor： Hiraku CHAKIHARA ,  Yasushi ISHII

IPC: H01L29/792

CPC classification number: H01L27/11575 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823835 ,  H01L27/0922 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11546 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11568 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7881 ,  H01L29/792

Abstract: Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the CG shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region.

Abstract translation: 提供了一种提高包括分离栅结构中的非易失性存储单元的半导体器件的制造成品率的技术。 形成CG分流部的选择栅电极，使得位于馈电区域的CG分流部的选择栅电极的半导体衬底的主表面的第二高度d2低于选择区域的第一高度d1 栅极电极从存储单元形成区域中的半导体衬底的主表面。