公开(公告)号：US20200266821A1

公开(公告)日：2020-08-20

申请号：US15929520

申请日：2020-05-07

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana SAHU ,  Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Hyeokjin LIM ,  Mickael MALABRY ,  Mukul GUPTA

IPC: H03K19/0948 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

公开(公告)号：US20190252408A1

公开(公告)日：2019-08-15

申请号：US15895094

申请日：2018-02-13

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin LIM ,  Xiangdong CHEN ,  Renukprasad HIREMATH ,  Rui LI ,  Venugopal BOYNAPALLI

IPC: H01L27/118 ,  H01L21/768 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L2027/11816 ,  H01L2027/11855 ,  H01L2027/11866 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: A semiconductor die includes a first diffusion region and a plurality of gates extending across the diffusion region. The plurality of gates are substantially parallel to each other. An interconnect layer above the diffusion region and plurality of gates includes a plurality of signal traces extending in a direction substantially perpendicular to the gates. At least two of the plurality of signal traces are located directly above the diffusion region such that at intersections of two gates with two separate signal traces are in the active transistor region, that is the portion of the gate extending over the diffusion region. Gate contacts coupling the two gates to the two separate signal traces are staggered by coupling to different signal traces.

公开(公告)号：US20190173473A1

公开(公告)日：2019-06-06

申请号：US16267289

申请日：2019-02-04

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana SAHU ,  Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Hyeokjin LIM ,  Mickael MALABRY ,  Mukul GUPTA

IPC: H03K19/0948 ,  H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  H01L27/118

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

公开(公告)号：US20180158506A1

公开(公告)日：2018-06-07

申请号：US15370892

申请日：2016-12-06

Applicant: QUALCOMM Incorporated

Inventor： Dorav KUMAR ,  Venkat NARAYANAN ,  Bilal ZAFAR ,  Seid Hadi RASOULI ,  Venugopal BOYNAPALLI

IPC: G11C11/4094 ,  G11C11/4076 ,  G06F1/12 ,  G06F1/06

CPC classification number: G11C11/4094 ,  G06F1/06 ,  G06F1/12 ,  G06F13/1689 ,  G11C7/222 ,  G11C11/4076

Abstract: The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gated clock. Additionally, the memory clock has a wider pulse width than the reference clock. In an example, the single stage logic gate comprises a pull-up circuit configured to pull-up the memory clock, and a pull-down circuit coupled to pull-down the memory clock. In an example, the pull-up and the pull-down circuits are configured to be controlled by the reference clock, a delayed reference clock, and a gating signal. An example further includes a delay circuit configured to generate the delayed reference clock from the reference clock. An example further includes a latch configured to generate the gating signal.