公开(公告)号：US10157153B2

公开(公告)日：2018-12-18

申请号：US15014158

申请日：2016-02-03

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Eyal Skulsky ,  Shaul Yohai Yifrach

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/16 ,  G06F13/40 ,  G06F12/14 ,  G06F13/38 ,  G06F21/85 ,  G06F21/60

Abstract: Aspects disclosed in the detailed description include inline cryptographic engine (ICE) for peripheral component interconnect express (PCIe). In this regard, in one aspect, an ICE is provided in a PCIe root complex (RC) in a host system. The PCIe RC is configured to receive at least one transport layer packet (TLP), which includes a TLP prefix, from a storage device. In a non-limiting example, the TLP prefix includes transaction-specific information that may be used by the ICE to provide data encryption and decryption. By providing the ICE in the PCIe RC and receiving the transaction-specific information in the TLP prefix, it is possible to encrypt and decrypt data in the PCIe RC in compliance with established standards, thus ensuring adequate protection during data exchange between the PCIe RC and the storage device.

公开(公告)号：US10042777B2

公开(公告)日：2018-08-07

申请号：US15084886

申请日：2016-03-30

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Shaul Yohai Yifrach ,  Thomas Zeng

IPC: G06F12/10 ,  G06F12/1027 ,  G06F3/06 ,  G06F12/1081 ,  G06F13/28 ,  G06F12/0891

Abstract: Hardware-based translation lookaside buffer (TLB) invalidation techniques are disclosed. A host system is configured to exchange data with a peripheral component interconnect express PCIE) endpoint (EP). A memory management unit (MMU), which is a hardware element, is included in the host system to provide address translation according to at least one TLB. In one aspect, the MMU is configured to invalidate the at least one TLB in response to receiving at least one TLB invalidation command from the PCIE EP. In another aspect, the PCIE EP is configured to determine that the at least one TLB needs to be invalidated and provide the TLB invalidation command to invalidate the at least one TLB. By implementing hardware-based TLB invalidation in the host system, it is possible to reduce TLB invalidation delay, thus leading to increased data throughput, reduced power consumption, and improved user experience.

公开(公告)号：US20180041431A1

公开(公告)日：2018-02-08

申请号：US15226383

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Shaul Yohai Yifrach ,  Tomer Rafael Ben-Chen ,  Amit Gil ,  Dan Gilboa Waizman ,  Deepak Jindal

IPC: H04L12/713 ,  H04L29/12 ,  H04L12/725 ,  H04L12/863

CPC classification number: H04L45/586 ,  H04L45/306 ,  H04L47/624 ,  H04L61/2521 ,  H04L69/22 ,  H04L69/321

Abstract: A virtualized Internet Protocol (IP) packet processing system is provided. In this regard, in one aspect, a computing circuit for processing IP packets is shared among a plurality of virtual clients. The computing circuit includes a plurality of hardware functional blocks each configured to perform a predefined IP packet processing function. In another aspect, a virtual channel is created for each of the virtual clients and assigned with one or more of the hardware functional blocks. In this regard, IP packets associated with each of the virtual clients may be processed by respective assigned hardware functional blocks based on a specified processing sequence. By sharing the computing circuit among the virtual clients and assigning respective hardware functional blocks to each virtual client, it is possible to optimize processing efficiency of the computing circuit, thus improving throughput, latency, and power consumption of the virtualized IP packet processing system.

公开(公告)号：US20170220494A1

公开(公告)日：2017-08-03

申请号：US15014158

申请日：2016-02-03

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Eyal Skulsky ,  Shaul Yohai Yifrach

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/14 ,  G06F13/40

CPC classification number: G06F13/1673 ,  G06F12/1408 ,  G06F12/1466 ,  G06F13/385 ,  G06F13/4068 ,  G06F13/4282 ,  G06F21/602 ,  G06F21/85 ,  G06F2212/402

Abstract: Aspects disclosed in the detailed description include inline cryptographic engine (ICE) for peripheral component interconnect express (PCIe). In this regard, in one aspect, an ICE is provided in a PCIe root complex (RC) in a host system. The PCIe RC is configured to receive at least one transport layer packet (TLP), which includes a TLP prefix, from a storage device. In a non-limiting example, the TLP prefix includes transaction-specific information that may be used by the ICE to provide data encryption and decryption. By providing the ICE in the PCIe RC and receiving the transaction-specific information in the TLP prefix, it is possible to encrypt and decrypt data in the PCIe RC in compliance with established standards, thus ensuring adequate protection during data exchange between the PCIe RC and the storage device.