GATE BOOSTED LOW DROP REGULATOR
    21.
    发明申请

    公开(公告)号:US20170285675A1

    公开(公告)日:2017-10-05

    申请号:US15086956

    申请日:2016-03-31

    CPC classification number: G05F1/575

    Abstract: In certain aspects, a voltage regulator includes a pass transistor having a drain coupled to an input of the voltage regulator, a source coupled to an output of the voltage regulator, and a gate. The voltage regulator also includes an amplifier having a first input coupled to a reference voltage, a second input coupled to a feedback voltage, and an output, wherein the feedback voltage is approximately equal to or proportional to a voltage at the output of the voltage regulator. The voltage regulator further includes a voltage booster having an input coupled to the output of the amplifier and an output coupled to the gate of the pass transistor, wherein the voltage booster is configured to boost a voltage at the input of the voltage booster to generate a boosted voltage, and to output the boosted voltage at the output of the voltage booster.

    Gate boosted low drop regulator
    22.
    发明授权

    公开(公告)号:US09778672B1

    公开(公告)日:2017-10-03

    申请号:US15086956

    申请日:2016-03-31

    CPC classification number: G05F1/575

    Abstract: In certain aspects, a voltage regulator includes a pass transistor having a drain coupled to an input of the voltage regulator, a source coupled to an output of the voltage regulator, and a gate. The voltage regulator also includes an amplifier having a first input coupled to a reference voltage, a second input coupled to a feedback voltage, and an output, wherein the feedback voltage is approximately equal to or proportional to a voltage at the output of the voltage regulator. The voltage regulator further includes a voltage booster having an input coupled to the output of the amplifier and an output coupled to the gate of the pass transistor, wherein the voltage booster is configured to boost a voltage at the input of the voltage booster to generate a boosted voltage, and to output the boosted voltage at the output of the voltage booster.

    Fractional phase locked loop (PLL) architecture
    23.
    发明授权
    Fractional phase locked loop (PLL) architecture 有权
    分数锁相环(PLL)架构

    公开(公告)号:US09577646B1

    公开(公告)日:2017-02-21

    申请号:US14820894

    申请日:2015-08-07

    CPC classification number: H03K21/10 H03L7/18 H03L7/197 H03L7/1974 H03L7/1976

    Abstract: In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.

    Abstract translation: 在一个实施例中,用于分频的方法包括将模数信号向上传播到一级级联分频器级从最后一级分频级到第一分频级,并且对于每个分频级,产生相应的本地 当模数信号传播到分频器级之后的负载信号。 该方法还包括对于每个分频器级,基于相应的本地负载信号将一个或多个相应的控制位输入到分频器级,所述一个或多个相应的控制位设置分频器级的分频器值。

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