Patched shading in graphics processing

    公开(公告)号:US11200733B2

    公开(公告)日:2021-12-14

    申请号:US16711098

    申请日:2019-12-11

    Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.

    BIN FILTERING
    23.
    发明申请

    公开(公告)号:US20210383545A1

    公开(公告)日:2021-12-09

    申请号:US16892096

    申请日:2020-06-03

    Abstract: Methods, systems, and devices for graphics processing are described. A device may receive an image including a set of pixels. The device may render a first subset of pixels in each bin of a set of bins during a first rendering pass, and defer rendering a second subset of pixels and a third subset of pixels in each bin of the set of bins during the first rendering pass. The second subset of pixels may include edge pixels and the third subset of pixels may be between the first subset of pixels and the second subset of pixels. The device may render the second subset of pixels and the third subset of pixels in each bin of the set of bins during a second rendering pass based on rendering the first subset of pixels. The device may then output the image based on the first and second rendering pass.

    Out of order wave slot release for a terminated wave

    公开(公告)号:US11094032B2

    公开(公告)日:2021-08-17

    申请号:US16734252

    申请日:2020-01-03

    Abstract: Methods, systems, and devices for image processing are described. A device may determine, based on a test operation, to terminate a first wave associated with a first slot of a set of slots. The device may update a terminated wave bit associated with the first slot based on the determination to terminate the first wave. In some aspects, the device may update a number of invocations field associated with the first wave based on the determination to terminate the first wave. The device may release the first slot based on updating the terminated wave bit and the number of invocations field. In some examples, the device may output the number of invocations field to a rendering backend of the device based on the terminated wave bit.

    BIN RESOLVE WITH CONCURRENT RENDERING OF A NEXT BIN

    公开(公告)号:US20200273142A1

    公开(公告)日:2020-08-27

    申请号:US16282003

    申请日:2019-02-21

    Abstract: The described techniques provide for bin-based rendering where the scene geometry in a frame is subdivided into bins or tiles, and bins are resolved concurrently with the rendering of a next bin. For example, a graphics processing unit (GPU) may process an entire image and sort transactions (e.g., rasterized primitives, such as triangles) into bins. For the rendering of each transaction, a device may identify a memory address of a memory block (e.g., a unit or portion of internal GPU memory (GMEM)) the transaction will be written (i.e., rendered) to. The device may thus prepare the memory block for rendering (e.g., by performing a resolve operation, a clear operation, or an unresolve operation on the memory block), such that the memory block is prepared prior to rendering of the particular transaction. As such, transactions of a bin may be resolved concurrently with rendering of transactions of a next bin.

    MEMORY ADDRESS FLIPPING TO DETERMINE DATA CONTENT INTEGRITY IN GPU SUB-SYSTEM

    公开(公告)号:US20190139263A1

    公开(公告)日:2019-05-09

    申请号:US15804707

    申请日:2017-11-06

    Abstract: Techniques of this disclosure may include processing data using one or more processors to produce a first image, including storing intermediate first results of processing the data in at least one internal memory of the one or more processors according to a first memory access pattern, processing the data using the one or more processors to produce a second image, including storing intermediate second results of processing the data in the at least one internal memory of the one or more processors according to a second memory access pattern, wherein the second memory access pattern is different than the first memory access pattern, comparing the first image to the second image, and generating an interrupt if the comparison indicates that the first image is different than the second image.

Patent Agency Ranking