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公开(公告)号:US12079897B2
公开(公告)日:2024-09-03
申请号:US17935031
申请日:2022-09-23
Applicant: QUALCOMM Incorporated
Inventor: Kalyan Kumar Bhiravabhatla , Andrew Evan Gruber , Rahul Sunil Kukreja , Vishwanath Shashikant Nikam , Tao Wang , Jian Liang
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005 , G06T15/405
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.
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公开(公告)号:US11200733B2
公开(公告)日:2021-12-14
申请号:US16711098
申请日:2019-12-11
Applicant: QUALCOMM Incorporated
Inventor: Vineet Goel , Andrew Evan Gruber , Donghyun Kim
Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.
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公开(公告)号:US20210383545A1
公开(公告)日:2021-12-09
申请号:US16892096
申请日:2020-06-03
Applicant: QUALCOMM Incorporated
Inventor: Jian Liang , Andrew Evan Gruber , Tao Wang , Srihari Babu Alla , Kalyan Kumar Bhiravabhatla , Jonnala Gadda Nagendra Kumar , William Licea-Kane , Fredrick Alan Hickman
Abstract: Methods, systems, and devices for graphics processing are described. A device may receive an image including a set of pixels. The device may render a first subset of pixels in each bin of a set of bins during a first rendering pass, and defer rendering a second subset of pixels and a third subset of pixels in each bin of the set of bins during the first rendering pass. The second subset of pixels may include edge pixels and the third subset of pixels may be between the first subset of pixels and the second subset of pixels. The device may render the second subset of pixels and the third subset of pixels in each bin of the set of bins during a second rendering pass based on rendering the first subset of pixels. The device may then output the image based on the first and second rendering pass.
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公开(公告)号:US11194683B2
公开(公告)日:2021-12-07
申请号:US16815718
申请日:2020-03-11
Applicant: QUALCOMM Incorporated
Inventor: Rahul Gulati , Andrew Evan Gruber , Brendon Lewis Johnson , Jay Chunsup Yun , Donghyun Kim , Alex Kwang Ho Jong , Anshuman Saxena
IPC: G06F11/00 , G06F11/22 , G06F11/07 , G06T15/00 , G06T1/20 , G06F11/277 , G01R31/3187 , G01R31/317
Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.
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公开(公告)号:US11094032B2
公开(公告)日:2021-08-17
申请号:US16734252
申请日:2020-01-03
Applicant: QUALCOMM INCORPORATED
Inventor: Yun Du , Chun Yu , Andrew Evan Gruber , Zilin Ying , Baoguang Yang
Abstract: Methods, systems, and devices for image processing are described. A device may determine, based on a test operation, to terminate a first wave associated with a first slot of a set of slots. The device may update a terminated wave bit associated with the first slot based on the determination to terminate the first wave. In some aspects, the device may update a number of invocations field associated with the first wave based on the determination to terminate the first wave. The device may release the first slot based on updating the terminated wave bit and the number of invocations field. In some examples, the device may output the number of invocations field to a rendering backend of the device based on the terminated wave bit.
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公开(公告)号:US20200273142A1
公开(公告)日:2020-08-27
申请号:US16282003
申请日:2019-02-21
Applicant: QUALCOMM Incorporated
Inventor: Shambhoo Khandelwal , Tao Wang , Shangmei Yu , Jing Gao , Jian Liang , Andrew Evan Gruber , Chun Yu
Abstract: The described techniques provide for bin-based rendering where the scene geometry in a frame is subdivided into bins or tiles, and bins are resolved concurrently with the rendering of a next bin. For example, a graphics processing unit (GPU) may process an entire image and sort transactions (e.g., rasterized primitives, such as triangles) into bins. For the rendering of each transaction, a device may identify a memory address of a memory block (e.g., a unit or portion of internal GPU memory (GMEM)) the transaction will be written (i.e., rendered) to. The device may thus prepare the memory block for rendering (e.g., by performing a resolve operation, a clear operation, or an unresolve operation on the memory block), such that the memory block is prepared prior to rendering of the particular transaction. As such, transactions of a bin may be resolved concurrently with rendering of transactions of a next bin.
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公开(公告)号:US10467774B2
公开(公告)日:2019-11-05
申请号:US15804707
申请日:2017-11-06
Applicant: QUALCOMM Incorporated
Inventor: Andrew Evan Gruber , Rahul Gulati , Brendon Lewis Johnson , Jay Chunsup Yun , Alex Kwang Ho Jong , Donghyun Kim
Abstract: Techniques of this disclosure may include processing data using one or more processors to produce a first image, including storing intermediate first results of processing the data in at least one internal memory of the one or more processors according to a first memory access pattern, processing the data using the one or more processors to produce a second image, including storing intermediate second results of processing the data in the at least one internal memory of the one or more processors according to a second memory access pattern, wherein the second memory access pattern is different than the first memory access pattern, comparing the first image to the second image, and generating an interrupt if the comparison indicates that the first image is different than the second image.
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公开(公告)号:US10445902B2
公开(公告)日:2019-10-15
申请号:US15377801
申请日:2016-12-13
Applicant: QUALCOMM Incorporated
Inventor: Andrew Evan Gruber , Serag GadelRab , Zhenbiao Ma , Meghal Varia , Tao Wang , Tom Longo , Mark Sternberg , Paul Chow
Abstract: Techniques are described in which a device is configured to retrieve a metadata buffer for rendering a sub-frame of a set of sub-frames for a frame. A data block of a data buffer is configured to store image data for rendering the sub-frame. In response to determining, based on the metadata buffer for rendering the sub-frame, that the sub-frame includes a color pattern, fixed color value, or combination thereof, the device refrains from retrieving the image data from the data block of the data buffer and determines the image data for rendering the sub-frame based on the metadata buffer.
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公开(公告)号:US20190196926A1
公开(公告)日:2019-06-27
申请号:US15850967
申请日:2017-12-21
Applicant: QUALCOMM Incorporated
Inventor: Alex Kwang Ho Jong , Jay Chunsup Yun , Donghyun Kim , Rahul Gulati , Brendon Lewis Johnson , Andrew Evan Gruber
IPC: G06F11/277 , G06T1/20 , G06T7/00 , G06F11/22
CPC classification number: G06F11/277 , G06F11/2236 , G06T1/20 , G06T7/0002 , G06T7/97 , G06T2207/30168
Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device operates in a first rendering mode to process graphics data to produce a first image. The GPU operates in a second rendering mode to process the graphics data to produce a second image. The computing device detects whether a fault has occurred in the GPU subsystem based at least in part on comparing the first image with the second image.
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公开(公告)号:US20190139263A1
公开(公告)日:2019-05-09
申请号:US15804707
申请日:2017-11-06
Applicant: QUALCOMM Incorporated
Inventor: Andrew Evan Gruber , Rahul Gulati , Brendon Lewis Johnson , Jay Chunsup Yun , Alex Kwang Ho Jong , Donghyun Kim
Abstract: Techniques of this disclosure may include processing data using one or more processors to produce a first image, including storing intermediate first results of processing the data in at least one internal memory of the one or more processors according to a first memory access pattern, processing the data using the one or more processors to produce a second image, including storing intermediate second results of processing the data in the at least one internal memory of the one or more processors according to a second memory access pattern, wherein the second memory access pattern is different than the first memory access pattern, comparing the first image to the second image, and generating an interrupt if the comparison indicates that the first image is different than the second image.
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