公开(公告)号：US20250044982A1

公开(公告)日：2025-02-06

申请号：US18364277

申请日：2023-08-02

Applicant: QUALCOMM Incorporated

Inventor： Sai Naresh GAJAPAKA ,  Chintalapati BHARATH SAI VARMA ,  Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Vamsi Krishna SAMBANGI

IPC: G06F3/06

Abstract: Aspects relate to interrupting memory access during background operations of a memory device. In one example a memory device includes a memory controller to initiate a write buffer flush operation. A bus interface is coupled to a main memory and to a write buffer to receive a write command from a host during the write buffer flush operation. The memory controller initiates the write buffer flush operation, suspends the write buffer flush operation in response to the write command, sends a last flushed address of the write buffer from the memory device to the host through the bus interface, and unmaps a portion of the write buffer using the last flushed address.

公开(公告)号：US20250044945A1

公开(公告)日：2025-02-06

申请号：US18365700

申请日：2023-08-04

Applicant: QUALCOMM Incorporated

Inventor： Pratibind Kumar JHA ,  Manish GARG ,  Prakhar SRIVASTAVA ,  Santhosh Reddy AKAVARAM ,  Hung VUONG ,  Abhishek GHOSH ,  Shubham KANWAL

IPC: G06F3/06 ,  G06F12/0802 ,  G06F12/1009

Abstract: A host device includes system memory that includes a logical-to-physical (L2P) cache and a second cache. The host device also includes a host controller interface (HCI) configured to be coupled to a flash memory device. The HCI is configured to determine that a particular region of a L2P address mapping table is to be removed from the L2P cache. The L2P address mapping table is configured to include mappings between logical memory addresses and physical memory addresses of the flash memory device. The HCI is also configured to identify a particular sub-region of the particular region having an access metric that satisfies a retention criterion. The HCI is further configured to store the particular sub-region into the second cache. The HCI is also configured to remove the particular region from the L2P cache.

公开(公告)号：US20240354141A1

公开(公告)日：2024-10-24

申请号：US18303101

申请日：2023-04-19

Applicant: QUALCOMM INCORPORATED

Inventor： Prakhar SRIVASTAVA ,  Santhosh Reddy AKAVARAM ,  Ravindranath DODDI ,  Radhakrishna MUGADA

IPC: G06F9/455 ,  G06F13/42

CPC classification number: G06F9/45558 ,  G06F13/4221 ,  G06F2009/45579 ,  G06F2009/45595

Abstract: A multi-lane data communication link, such as a PCIe link, may be configured as virtual links. Each virtual link may correspond to a unique subset of the lanes. Data packets provided by multiple virtual machines and associated virtual functions may be buffered in transmit queues. Each transmit queue may correspond to a unique one of the virtual links. The data may be provided from each of the transmit queues to data transmitting circuitry coupled to active lanes.