公开(公告)号：US08928365B2

公开(公告)日：2015-01-06

申请号：US13658778

申请日：2012-10-23

Applicant: QUALCOMM Incorporated

Inventor： Miao Li ,  Jingcheng Zhuang ,  Yan Hu ,  Xiaoliang Bai ,  Jing Kang

IPC: H03K3/00

CPC classification number: H03K19/017554 ,  H03K19/0005

Abstract: An output driver for electrostatic discharge (ESD) protection includes a first pair of stacked metal oxide semiconductor field-effect transistor (MOS) devices coupled between a power terminal and a first differential output terminal. The output driver also includes a second pair of stacked MOS devices coupled between a second differential output terminal and a ground terminal.

Abstract translation: 用于静电放电（ESD）保护的输出驱动器包括耦合在电源端子和第一差分输出端子之间的第一对堆叠金属氧化物半导体场效应晶体管（MOS）器件。 输出驱动器还包括耦合在第二差分输出端子和接地端子之间的第二对堆叠MOS器件。

公开(公告)号：US20140256276A1

公开(公告)日：2014-09-11

申请号：US13784821

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Miao Li ,  Xiaohua Kong ,  Jingcheng Zhuang ,  Wei Wang

IPC: H04B1/18

CPC classification number: H04B3/50 ,  H04B3/30

Abstract: Techniques for accommodating an incoming signal at a front-end receiver via AC-coupling or DC-coupling are described herein. In one aspect, a front-end receiver comprises a differential input with a first data line and a second data line for receiving an incoming signal. The front-end receiver also comprises an AC-coupled switch coupled to the differential input, wherein the AC-coupled switch is configured to both perform high-pass filtering on the incoming signal and offset the filtered incoming signal with a DC-offset voltage if an AC-coupling mode of the receiver is enabled. The front-end receiver further comprises a DC-coupled switch coupled to the differential input, wherein the DC-coupled switch is configured to shift a common-mode voltage of the incoming signal if a DC-coupling mode of the receiver is enabled.

Abstract translation: 这里描述了用于通过AC耦合或DC耦合在前端接收器处容纳输入信号的技术。 一方面，前端接收机包括具有第一数据线的差分输入和用于接收输入信号的第二数据线。 前端接收器还包括耦合到差分输入的AC耦合开关，其中AC耦合开关被配置为对输入信号执行高通滤波，并且通过DC偏移电压偏移滤波的输入信号，如果 接收器的AC耦合模式被使能。 前端接收器还包括耦合到差分输入的DC耦合开关，其中如果接收器的DC耦合模式被使能，则DC耦合开关被配置为移位输入信号的共模电压。

公开(公告)号：US20140111250A1

公开(公告)日：2014-04-24

申请号：US13658778

申请日：2012-10-23

Applicant: QUALCOMM INCORPORATED

Inventor： Miao Li ,  Jingcheng Zhuang ,  Yan Hu ,  Xiaoliang Bai ,  Jing Kang

IPC: H03K3/00

CPC classification number: H03K19/017554 ,  H03K19/0005

Abstract: An output driver for electrostatic discharge (ESD) protection includes a first pair of stacked metal oxide semiconductor field-effect transistor (MOS) devices coupled between a power terminal and a first differential output terminal. The output driver also includes a second pair of stacked MOS devices coupled between a second differential output terminal and a ground terminal.

Abstract translation: 用于静电放电（ESD）保护的输出驱动器包括耦合在电源端子和第一差分输出端子之间的第一对堆叠金属氧化物半导体场效应晶体管（MOS）器件。 输出驱动器还包括耦合在第二差分输出端子和接地端子之间的第二对堆叠MOS器件。

公开(公告)号：US11139843B1

公开(公告)日：2021-10-05

申请号：US16927537

申请日：2020-07-13

Applicant: QUALCOMM Incorporated

Inventor： Miao Li ,  Jie Xu ,  Yu Song

IPC: H04L27/00 ,  H04B1/04 ,  H03K19/0185

Abstract: Certain aspects of the present disclosure generally relate to a driver circuit for a serializer/deserializer (SerDes) transmitter and techniques for operating such a driver circuit. One example driver circuit generally includes a pre-driver circuit, an output stage circuit, and a common-gate buffer circuit coupled between an output of the pre-driver circuit and a first input of the output stage circuit.

公开(公告)号：US10084621B2

公开(公告)日：2018-09-25

申请号：US15422050

申请日：2017-02-01

Applicant: QUALCOMM Incorporated

Inventor： Yu Song ,  Zhi Zhu ,  Miao Li ,  Li Sun ,  Deqiang Song ,  Chia Heng Chang

IPC: H03D3/18 ,  H03D3/24 ,  H04L25/03 ,  H04L12/26 ,  H04L27/00

Abstract: Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

公开(公告)号：US09722828B2

公开(公告)日：2017-08-01

申请号：US14862677

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Li Sun ,  Xiaohua Kong ,  Zhi Zhu ,  Miao Li ,  Dong Ren

IPC: H04L25/00 ,  H04L27/01 ,  H04L25/03 ,  H04L25/02

CPC classification number: H04L27/01 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/03006 ,  H04L25/03146 ,  H04L25/03878

Abstract: In one embodiment, a receiver comprises a latch configured to receive a data signal and to latch symbols of the received data signal, and a decision feedback equalizer. The decision feedback equalizer comprises a first feedback capacitor having first and second terminals, the first terminal being coupled to a first internal node of the latch. The decision feedback equalizer also comprises a first plurality of switches configured to alternatively couple the second terminal of the first feedback capacitor to a first feedback signal and a ground, the first feedback signal having a first voltage that is a function of a bit decision corresponding to a first previous symbol in the data signal preceding a current symbol in the data signal.

公开(公告)号：US20170085403A1

公开(公告)日：2017-03-23

申请号：US14862677

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Li Sun ,  Xiaohua Kong ,  Zhi Zhu ,  Miao Li ,  Dong Ren

IPC: H04L27/01 ,  H04L25/03

CPC classification number: H04L27/01 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/03006 ,  H04L25/03146 ,  H04L25/03878

Abstract: In one embodiment, a receiver comprises a latch configured to receive a data signal and to latch symbols of the received data signal, and a decision feedback equalizer. The decision feedback equalizer comprises a first feedback capacitor having first and second terminals, the first terminal being coupled to a first internal node of the latch. The decision feedback equalizer also comprises a first plurality of switches configured to alternatively couple the second terminal of the first feedback capacitor to a first feedback signal and a ground, the first feedback signal having a first voltage that is a function of a bit decision corresponding to a first previous symbol in the data signal preceding a current symbol in the data signal.

公开(公告)号：US20160079942A1

公开(公告)日：2016-03-17

申请号：US14486885

申请日：2014-09-15

Applicant: QUALCOMM Incorporated

Inventor： Miao Li ,  Li Sun ,  Zhi Zhu

IPC: H03F3/45 ,  H04B1/16 ,  H04L25/02 ,  H03F3/183

CPC classification number: H03F3/45071 ,  H03F3/183 ,  H03F3/45179 ,  H03F3/45677 ,  H03F3/45713 ,  H03F2200/129 ,  H03F2200/255 ,  H03F2200/36 ,  H03F2200/453 ,  H03F2203/45008 ,  H03F2203/45078 ,  H03F2203/45112 ,  H03F2203/45302 ,  H03F2203/45306 ,  H03F2203/45418 ,  H03F2203/45422 ,  H03F2203/45424 ,  H04B1/16 ,  H04L25/0272

Abstract: In one embodiment, a receiver comprises a differential common-gate amplifier having a differential input and a differential output, wherein the differential input comprises a first input and a second input, and the differential common-gate amplifier is configured to amplify an input differential signal at the differential input into an amplified differential signal at the differential output. The receiver also comprises a common-mode voltage sensor configured to sense a common-mode voltage of the input differential signal, a replica circuit configured to generate a replica voltage that tracks a direct current (DC) voltage at at least one of the first and second inputs, and a comparator configured to compare the sensed common-mode voltage with the replica voltage, and to adjust a first bias voltage input to the differential common-gate amplifier based on the comparison, wherein the DC voltage depends on the first bias voltage.

Abstract translation: 在一个实施例中，接收机包括具有差分输入和差分输出的差分共栅放大器，其中差分输入包括第一输入和第二输入，并且差分共栅放大器被配置为放大输入差分信号 在差分输入处的差分输出处的放大的差分信号。 接收机还包括被配置为感测输入差分信号的共模电压的共模电压传感器，复制电路被配置为产生在第一和第二和第二至少一个处跟踪直流（DC）电压的复制电压 第二输入和比较器，被配置为将感测的共模电压与复制电压进行比较，并且基于比较来调整输入到差分公共栅放大器的第一偏置电压，其中DC电压取决于第一偏置电压 。