公开(公告)号：US20180173490A1

公开(公告)日：2018-06-21

申请号：US15895965

申请日：2018-02-13

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Amit Gil ,  Oded Schnitzer

IPC: G06F3/16 ,  G10K11/16 ,  G10L19/018

CPC classification number: G06F3/165 ,  G10K11/16 ,  G10L19/012 ,  G10L19/018 ,  H03G3/341 ,  H03G3/348

Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

公开(公告)号：US20160320823A1

公开(公告)日：2016-11-03

申请号：US14702175

申请日：2015-05-01

Applicant: QUALCOMM Incorporated

Inventor： Nir Gerber ,  Lior Amarilio ,  Amit Gil

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3253 ,  G06F13/385 ,  G06F2213/0042 ,  Y02D10/151 ,  Y02D50/20

Abstract: Aspects disclosed in the detailed description include scheduled universal serial bus (USB) low-power operations. In this regard, in one aspect, a USB host controller determines a low-power operation schedule for a USB client device. The low-power operation schedule comprises one or more scheduled low-power operation periods, each corresponding to a respective entry time and a respective exit time. The USB host controller communicates the low-power operation schedule to the USB client device using one or more USB standard packets. By scheduling the one or more scheduled low-power operation periods with respective entry and exit times, the USB host controller or the USB client controller is able to start and end the one or more scheduled low-power operation periods without incurring additional signaling, thus improving efficiency of the USB low-power operation. Further, by communicating the low-power operation schedule using USB standard packets, it is possible to preserve compatibility with USB standards.

Abstract translation: 在详细描述中公开的方面包括调度的通用串行总线（USB）低功率操作。 在这方面，在一方面，USB主机控制器确定USB客户端设备的低功率操作调度。 低功率操作调度包括一个或多个调度的低功率操作周期，每个周期对应于相应的进入时间和相应的退出时间。 USB主机控制器使用一个或多个USB标准数据包将低功耗操作计划传送到USB客户端设备。 通过调度具有相应进入和退出时间的一个或多个调度的低功率操作时段，USB主机控制器或USB客户端控制器能够开始和结束一个或多个调度的低功率操作时段，而不会产生额外的信号，因此 提高USB低功耗操作的效率。 此外，通过使用USB标准分组传送低功率运行调度表，可以保持与USB标准的兼容性。

公开(公告)号：US20160259702A1

公开(公告)日：2016-09-08

申请号：US15060221

申请日：2016-03-03

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  James Lionel Panian ,  George Alan Wiley ,  Amit Gil

IPC: G06F11/30 ,  G06F15/17 ,  G06F1/32 ,  G06F9/44 ,  G06F15/78

CPC classification number: G06F11/3051 ,  G06F1/3209 ,  G06F1/3278 ,  G06F9/4418 ,  G06F11/3041 ,  G06F15/17 ,  G06F15/7807 ,  Y02D10/157

Abstract: System, methods, and apparatuses are described that facilitate a first device to transmit/retransmit a message to a second device. The first device transmits a first message to the second device. The first device then receives a second message and identifies a hit of the second message indicating an originator of the second message. If the bit indicates the first device as the originator of the second message, then the second message is an echo of the first message, Reception of the echo indicates that the second device is in a sleep state. Accordingly, the first device waits for the second device to wake and retransmits the first message to the second device to ensure that any packets lost during the original transmission of the first message (when the second device was asleep) are now retransmitted while the second device is known to be awake.

Abstract translation: 描述了便于第一设备向第二设备发送/重发消息的系统，方法和设备。 第一设备向第二设备发送第一消息。 然后，第一设备接收第二消息并识别指示第二消息的发起者的第二消息的命中。 如果该比特指示第一个设备作为第二个消息的发起者，则第二个消息是第一个消息的回应，回应的接收表明第二个设备处于睡眠状态。 因此，第一设备等待第二设备唤醒并将第一消息重新发送到第二设备，以确保在第一消息的原始传输期间（当第二设备睡着时）丢失的任何分组现在在第二设备 已知醒来。

公开(公告)号：US20150143022A1

公开(公告)日：2015-05-21

申请号：US14080852

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Amit Gil

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0238 ,  G06F13/4068 ,  G06F2212/7207

Abstract: Removable memory card discrimination systems and methods are disclosed. In particular, exemplary embodiments discriminate between secure digital (SD) cards and other removable memory cards that comply with the SD form factor, but support the Universal Flash Storage (UFS) protocol. That is, a host may have a receptacle that supports the SD card form factor and is configured to receive a device. In use, a removable memory card is inserted into the receptacle and, using an SD compliant interrogation signal, the host interrogates a common area on the card so inserted. The common area includes information related to capability descriptors of the card. An SD compliant card will respond with information such as capability descriptors about the SD protocol capabilities, while a UFS compliant card will respond with an indication that the card is UFS compliant. The host may then restart the communication with the card using the UFS protocol.

Abstract translation: 公开了可移动存储卡鉴别系统和方法。 特别地，示例性实施例区分安全数字（SD）卡和符合SD外形尺寸但支持通用闪存存储（UFS）协议的其他可移动存储卡。 也就是说，主机可以具有支持SD卡形状因子的插座，并且被配置为接收设备。 在使用中，将可移动存储卡插入插座中，并且使用SD兼容询问信号，主机询问插入的卡上的公共区域。 公共区域包括与卡的能力描述符相关的信息。 SD兼容卡将响应诸如关于SD协议能力的能力描述符的信息，而符合UFS的卡将响应该卡符合UFS的指示。 然后，主机可以使用UFS协议重新启动与该卡的通信。

公开(公告)号：US10963035B2

公开(公告)日：2021-03-30

申请号：US16155824

申请日：2018-10-09

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  James Lionel Panian ,  Richard Dominic Wietfeldt ,  Mohit Kishore Prasad ,  Amit Gil ,  Shaul Yohai Yifrach

IPC: G06F1/3234 ,  G06F13/40 ,  G06F13/10 ,  G06F1/3206

Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.

公开(公告)号：US10795400B2

公开(公告)日：2020-10-06

申请号：US15966077

申请日：2018-04-30

Applicant: QUALCOMM Incorporated

Inventor： Yiftach Benjamini ,  Amit Gil ,  Shaul Yohai Yifrach

IPC: G06F1/12 ,  G06F13/42

Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.

公开(公告)号：US10713199B2

公开(公告)日：2020-07-14

申请号：US16012532

申请日：2018-06-19

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Amit Gil ,  Sharon Graif

IPC: G06F13/364 ,  G06F1/08 ,  G06F3/16 ,  H04R3/00 ,  H04R3/12 ,  G06F13/42 ,  G06F1/12

Abstract: System, methods and apparatus are described that can improve available bandwidth on a SoundWire bus without increasing the number of pins used by the SoundWire bus. A method performed at a master device coupled to a SoundWire bus includes providing a clock signal by a first master device over a clock line of a SoundWire bus to a first slave device and a second slave device coupled to the SoundWire bus, transmitting first control information from the first master device to the first slave device over a first data line of the SoundWire bus, and transmitting second control information from the first master device to the second slave device over a second data line of the SoundWire bus. The first control information may be different from the second control information and is transmitted concurrently with the second control information.

公开(公告)号：US10417161B2

公开(公告)日：2019-09-17

申请号：US16219698

申请日：2018-12-13

Applicant: QUALCOMM Incorporated

Inventor： Helena Deirdre O'Shea ,  Lalan Jee Mishra ,  Amit Gil ,  Gary Chang ,  Mohit Kishore Prasad ,  Richard Dominic Wietfeldt ,  Vinay Jain

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: In a device comprising a serial bus and a plurality of devices, register/address mappings and/or unique group identifiers are used to convey additional information in messages/datagrams over the serial bus without explicitly sending such information in the message/datagram. Such register/address mappings may be done beforehand, and in conjunction with group-specific identifiers, may reduce transmission latency by keeping the size of the messages/datagrams small. Since all devices on the serial bus have prior knowledge of such register/address mappings and/or group-specific identifiers, recipient devices are able to infer information from the group-specific identifiers and/or register/address sent in each message/datagram that is not explicitly sent within such message/datagram.

公开(公告)号：US10310585B2

公开(公告)日：2019-06-04

申请号：US15726566

申请日：2017-10-06

Applicant: QUALCOMM Incorporated

Inventor： Shaul Yohai Yifrach ,  Amit Gil ,  James Lionel Panian ,  Ofer Rosenberg ,  Richard Dominic Wietfeldt

IPC: G06F1/32 ,  G06F13/42 ,  G06F1/3234 ,  G06F13/40 ,  H01L23/29 ,  H04L12/931

Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.

公开(公告)号：US20190058780A1

公开(公告)日：2019-02-21

申请号：US15678531

申请日：2017-08-16

Applicant: QUALCOMM Incorporated

Inventor： Amit Gil ,  Shaul Yohai Yifrach

IPC: H04L29/06 ,  G06F13/12 ,  H04L12/807 ,  H04L12/801

Abstract: Alternate acknowledgment (ACK) signals in a coalescing Transmission Control Protocol/Internet Protocol (TCP/IP) system are disclosed. In one aspect, a network interface card (NIC) examines packet payloads, and the NIC generates an ACK signal for a sending server before sending a coalesced packet to an internal processor. Further, the NIC may examine incoming packets and send an ACK signal to the internal processor for ACK signals that are received from the sending server before sending the coalesced packet to the internal processor. By extracting and sending the ACK signals before sending the corresponding payloads in the coalesced packet, latency that would otherwise be incurred waiting for the ACK signal is eliminated. Elimination of such latency may improve network performance and may provide power savings.