Abstract:
An improved back side illuminated (BSI) complementary metal oxide semiconductor (CMOS) image sensor, and associated methods, improve phase detecting capability. The BSI CMOS image sensor has an array of pixels that include a phase detecting pixel (PDP), a composite grid formed of a buried color filter array and composite metal/oxide grid, and a photodiode implant corresponding to the PDP. A PDP mask is fabricated with a deep trench isolation (DTI) structure proximate the PDP and positioned to mask at least part of the photodiode implant such that the PDP mask is positioned between the composite grid and the photodiode implant.
Abstract:
An image sensor includes a photodiode proximate to a front side of semiconductor material to accumulate image charge. A metal layer reflector structure is disposed in a dielectric layer proximate to the front side of the semiconductor material. A contact reflecting ring structure is disposed in the dielectric layer between the metal layer reflector structure and a contact etch stop layer disposed over the front side of the semiconductor material. The contact reflecting ring structure defines a portion of a light guide in the dielectric layer such that light that is directed through a back side of the semiconductor material, through the photodiode, and reflected from the metal layer reflector structure back through the photodiode is confined to remain within an interior of the contact reflecting ring structure when passing through the dielectric layer between the photodiode and the metal layer reflector structure.
Abstract:
An image sensor including a plurality of photodiodes disposed in a semiconductor layer and a plurality of deep trench isolation regions disposed in the semiconductor layer. The plurality of deep trench isolation regions include: (1) an oxide layer disposed on an inner surface of the plurality of deep trench isolation regions and (2) a conductive fill disposed in the plurality of deep trench isolation regions where the oxide layer is disposed between the semiconductor layer and the conductive fill. A plurality of pinning wells is also disposed in the semiconductor layer, and the plurality of pinning wells in combination with the plurality of deep trench isolation regions separate individual photodiodes in the plurality of photodiodes. A fixed charge layer is disposed on the semiconductor layer, and the plurality of deep trench isolation regions are disposed between the plurality of pinning wells and the fixed charge layer.
Abstract:
An image sensor including a plurality of photodiodes disposed in a semiconductor layer and a plurality of deep trench isolation regions disposed in the semiconductor layer. The plurality of deep trench isolation regions include: (1) an oxide layer disposed on an inner surface of the plurality of deep trench isolation regions and (2) a conductive fill disposed in the plurality of deep trench isolation regions where the oxide layer is disposed between the semiconductor layer and the conductive fill. A plurality of pinning wells is also disposed in the semiconductor layer, and the plurality of pinning wells in combination with the plurality of deep trench isolation regions separate individual photodiodes in the plurality of photodiodes. A fixed charge layer is disposed on the semiconductor layer, and the plurality of deep trench isolation regions are disposed between the plurality of pinning wells and the fixed charge layer.
Abstract:
Electrical Phase Detection Auto Focus. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor material. Each pixel includes a plurality of photodiodes configured to receive incoming light through an illuminated surface of the semiconductor material. The plurality of pixels includes at least one autofocusing phase detection (PDAF) pixel having: a first subpixel without a light shielding, and a second subpixel without the light shielding. Autofocusing of the image sensor is at least in part determined based on different electrical outputs of the first subpixel and the second sub pixels.
Abstract:
An image sensor includes an active pixel photodiode, a black pixel photodiode, a metal grid structure, a light shield, and a varying thickness dielectric layer. The varying thickness dielectric layer includes a first portion having a first dielectric layer thickness and a second portion having a second dielectric layer thickness different from the first dielectric layer thickness. The metal grid structure is disposed between the first portion of the varying thickness dielectric layer and a semiconductor material. The light shield is disposed between the second portion of the varying thickness dielectric layer and the black pixel photodiode.
Abstract:
An image sensor includes an active pixel photodiode, a black pixel photodiode, a metal grid structure, and a light shield. Each of the active pixel photodiode and the black pixel photodiode are disposed in a semiconductor material having a first side and a second side opposite the first side. The first side of the semiconductor material is disposed between the light shield and the black pixel photodiode. The metal grid structure includes a first multi-layer metal stack including a first metal and a second metal different from the first metal. The light shield includes a second multi-layer stack including the first metal and the second metal. A first thickness of the first multi-layer metal stack is less than a second thickness of the second multi-layer metal stack.
Abstract:
An image sensor comprises a pixel array of pixel cells. A pixel cell comprises a photodiode, a reset transistor, a transfer transistor, at least one source follower transistor, a sample and hold circuit, an active reset transistor, and a readout transistor. A readout circuitry reads out image data from each columns of pixel cells. A column differential amplifier in the readout circuitry feeds back a column reset drive voltage to each pixel cells arranged in the same column. Signal data of each pixel cells in the same column are read out globally when all the active reset transistors are switched off. Determined by switching configurations of each active reset transistors of pixel cells in the same column, noise data of each pixel cells in the same column are read out either globally or row-by-row. Final image data is achieved by applying the method of correlated double sampling (CDS).
Abstract:
An image sensor pixel array comprises a center region and two parallel edge regions, wherein the center region is between the two parallel edge regions. The center region comprises a plurality of image pixels disposed along first sub-array of rows and columns, wherein each of the plurality of image pixels comprises a first micro-lens (ML) formed at an offset position above a first light receiving element as a countermeasure for shortening of exit pupil distance of the image pixel in the center region, and each of the two parallel edge regions comprises a plurality of phase detection auto-focus (PDAF) pixels disposed along second sub-array of rows and columns, wherein each of the plurality of PDAF pixels comprises a second micro-lens (ML) formed at an alignment position above a second light receiving element; and at least one of the PDAF pixels is located at a distance away from center of the edge region to receive incident light along an injection tilt angle.
Abstract:
An image sensor includes a photodiode disposed in a semiconductor material to generate image charge in response to incident light, and a floating diffusion disposed in the semiconductor material proximate to the photodiode. A transfer transistor is coupled to the photodiode to transfer the image charge from the photodiode into the floating diffusion in response to a transfer signal applied to a transfer gate of the transfer transistor. A source follower transistor is coupled to the floating diffusion to amplify a charge on the floating diffusion. The source follower transistor includes a gate electrode including a semiconductor material having a first dopant type; a source electrode, having a second dopant type, disposed in the semiconductor material; a drain electrode, having the second dopant type, disposed in the semiconductor material; and a channel, having the second dopant type, disposed between the source electrode and the drain electrode.