公开(公告)号：US10090375B2

公开(公告)日：2018-10-02

申请号：US15450411

申请日：2017-03-06

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Cheng-Chou Hung

IPC: H01L27/01 ,  H01L49/02 ,  H01L23/00 ,  H01L23/66

Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A conductive structure is disposed on the conductive pad, and a passive device is also disposed on the conductive pad, wherein the passive device has a first portion located above the second passivation layer and a second portion passing through the second passivation layer. A solderability preservative film covers the first portion of the passive device, and an under bump metallurgy (UBM) layer covers the second portion of the passive device and a portion of the conductive structure.

公开(公告)号：US09806146B2

公开(公告)日：2017-10-31

申请号：US15367126

申请日：2016-12-01

Applicant: MEDIATEK INC.

Inventor： Bo-Shih Huang ,  Chien-Hui Chuang ,  Cheng-Chou Hung

IPC: H01L27/06 ,  H01L29/73 ,  H01L29/78 ,  H01L23/60 ,  H01L29/788 ,  H01L29/06 ,  H01L29/74 ,  H01L29/45 ,  H01L29/36

CPC classification number: H01L29/0603 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/45 ,  H01L29/7436

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; a first doped region of type one, doped in the well of type two; and a second doped region of type two, provided in the well of type one and the well of type two, not touching the first doped region of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

公开(公告)号：US09712130B2

公开(公告)日：2017-07-18

申请号：US14874888

申请日：2015-10-05

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Tung-Hsing Lee ,  Wei-Che Huang

IPC: H03H7/01 ,  H03H3/00 ,  H01P1/203 ,  H01P7/08

CPC classification number: H03H7/0115 ,  H01P1/20381 ,  H01P7/082 ,  H03H3/00

Abstract: An implementation of the invention is directed to a passive device cell having a substrate layer, and intermediary layer formed above the substrate layer, and a passive device formed above the intermediary layer. The intermediary layer includes a plurality of LC resonators and a plurality of segmented conductive lines, wherein the plurality of segmented conductive lines are disposed between the plurality of LC resonators.

公开(公告)号：US20170084685A1

公开(公告)日：2017-03-23

申请号：US15367126

申请日：2016-12-01

Applicant: MEDIATEK INC.

Inventor： Bo-Shih Huang ,  Chien-Hui Chuang ,  Cheng-Chou Hung

IPC: H01L29/06 ,  H01L29/36 ,  H01L29/45

CPC classification number: H01L29/0603 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/45 ,  H01L29/7436

Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; a first doped region of type one, doped in the well of type two; and a second doped region of type two, provided in the well of type one and the well of type two, not touching the first doped region of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.

公开(公告)号：US08796813B2

公开(公告)日：2014-08-05

申请号：US13797992

申请日：2013-03-12

Applicant: Mediatek Inc.

Inventor： Ming-Da Tsai ,  George Chien ,  Cheng-Chou Hung

IPC: H01L21/71 ,  H01L27/02

CPC classification number: H01L22/14 ,  H01L22/20

Abstract: A method for controlling an electrical property of a passive device during a fabrication of an integrated component includes providing a substrate, manufacturing the passive device on the substrate, measuring the electrical property of the passive device to obtain a measuring result, determining at least one layout pattern corresponding to at least one later manufacturing process by the measuring result for adjusting the electrical property of the passive device, and continuing the rest of the fabrication including the at least one later manufacturing process of the integrated component.

Abstract translation: 一种用于在集成部件的制造期间控制无源器件的电性能的方法包括提供衬底，在衬底上制造无源器件，测量无源器件的电性能以获得测量结果，确定至少一个布局 通过用于调整无源器件的电性能的测量结果对应于至少一个后续制造过程的模式，以及继续包括集成部件的至少一个后续制造过程的其余的制造。