公开(公告)号：US11113216B2

公开(公告)日：2021-09-07

申请号：US16810031

申请日：2020-03-05

Applicant: MediaTek Inc.

Inventor： Chia-Hao Hsu ,  Sen-Yu Cheng ,  Yan-Ting Chen ,  Po-Kai Chi

IPC: G06F13/24 ,  G06F1/3293 ,  G06F9/48

Abstract: A multi-processor system handles interrupts using a power and performance status of each processor and a usage scenario of each processor. The power and performance status is indicated by factors that affect power consumption and processor performance. The system identifies one of the processors for handling an interrupt based on a weighted combination of the factors. Each factor is weighted based on a usage scenario for which the interrupt was generated. The system then dispatches the interrupt to the identified one of the processors.

公开(公告)号：US20210074608A1

公开(公告)日：2021-03-11

申请号：US16989919

申请日：2020-08-11

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Sheng-Liang Kuo ,  Bo-Jiun Yang

IPC: H01L23/473 ,  H01L23/00 ,  H01L23/16

Abstract: A semiconductor package includes a substrate; a die mounted on a top surface of the substrate in a flip-chip fashion; and a lid mounted on the die and on a perimeter of the substrate. The lid includes a cover plate and four walls formed integral with the cover plate. A liquid-cooling channel is situated between the cover plate of the lid and a rear surface of the die for circulating a coolant relative to the semiconductor package.

公开(公告)号：US10089265B2

公开(公告)日：2018-10-02

申请号：US15186325

申请日：2016-06-17

Applicant: Mediatek Inc.

Inventor： Chia-Hao Hsu ,  Shun-Chih Yu ,  Sen-Yu Cheng

IPC: G06F13/24

Abstract: Systems, methods, and computer readable medium are provided that improve the management of interrupt requests in multiple processor computer systems. Interrupt requests can be classified into three categories and the structure of the categories provide for specifying a list that needs to be migrated. The list can contain only those interrupt requests that can be handled by some of the processors that will never unplug or based on affinity. When a processor is about to unplug, the computer system can migrate that list. The system can also manage the other interrupt requests.

公开(公告)号：US20170300427A1

公开(公告)日：2017-10-19

申请号：US15487402

申请日：2017-04-13

Applicant: MEDIATEK INC.

Inventor： Chien-Hung Lin ,  Ming-Ju Wu ,  Wei-Hao Chiao ,  Kun-Geng Lee ,  Shun-Chieh Chang ,  Ming-Ku Chang ,  Chia-Hao Hsu ,  Pi-Cheng Hsiao

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/128 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0862 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/602 ,  G06F2212/621

Abstract: A multi-processor system with cache sharing has a plurality of processor sub-systems and a cache coherence interconnect circuit. The processor sub-systems have a first processor sub-system and a second processor sub-system. The first processor sub-system includes at least one first processor and a first cache coupled to the at least one first processor. The second processor sub-system includes at least one second processor and a second cache coupled to the at least one second processor. The cache coherence interconnect circuit is coupled to the processor sub-systems, and used to obtain a cache line data from an evicted cache line in the first cache, and transfer the obtained cache line data to the second cache for storage.