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    LOW-POWER HIGHLY-ACCURATE PASSIVE MULTIPHASE CLOCK GENERATION SCHEME BY USING POLYPHASE FILTERS
    22.
    发明申请
    LOW-POWER HIGHLY-ACCURATE PASSIVE MULTIPHASE CLOCK GENERATION SCHEME BY USING POLYPHASE FILTERS 有权
    使用多相滤波器的低功耗高精度无源时钟产生方案

    公开(公告)号：US20130266103A1

    公开(公告)日：2013-10-10

    申请号：US13833407

    申请日：2013-03-15

    Applicant: Korea Advanced Institute of Science and Technology ,  TERASQUARE CO., LTD.

    Inventor： Hyeon Min Bae ,  Hyo Sup Won ,  Joon Young Lee ,  Jin Ho Park ,  Tae Ho Kim

    IPC: H04L7/00

    CPC classification number: H04L7/00 ,  H03L7/0807 ,  H03L7/0814 ,  H04L7/0337

    Abstract: Exemplary embodiments of the present invention relate to a low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters. An exemplary embodiment of the present invention may be low power phase-rotator-based 25 GB/s CDR architecture in case that half-rate reference clock is provided. It may be suitable for multi-lane scheme and incorporate phase interpolator with improved phase accuracy to make Nyquist-sampling clock phase. To improve the phase accuracy, poly phase filter may be used for converting 4-phase to 8-phase and interpolate adjacent 45 degree different phases. The linearity of phase rotator may be improved by proposed harmonic rejection poly phase filter (HRPPF) using the characteristic of notch filter response.

    Abstract translation: 本发明的示例性实施例涉及通过使用多相滤波器的低功率高精度无源多相时钟生成方案。 在提供半速率参考时钟的情况下，本发明的示例性实施例可以是基于低功率相位旋转器的25GB / s CDR架构。 它可能适用于多通道方案，并且并入具有提高的相位精度的相位内插器，以使奈奎斯特采样时钟相位。 为了提高相位精度，多相滤波器可用于将4相转换为8相，并内插相邻的45度相位。 通过使用陷波滤波器响应的特性，提出的谐波抑制多相滤波器（HRPPF）可以改善相位旋转器的线性度。

    Low-power CML-less transmitter architecture
    29.
    发明授权
    Low-power CML-less transmitter architecture 有权
    低功耗无CML发射机架构

    公开(公告)号：US09419736B2

    公开(公告)日：2016-08-16

    申请号：US13835530

    申请日：2013-03-15

    Applicant: Korea Advanced Institute of Science and Technology ,  TeraSquare Co., Ltd.

    Inventor： Hyeon Min Bae ,  Tae Hun Yoon ,  Jin Ho Park ,  Tae Ho Kim

    IPC: H04J3/04 ,  H03K19/173 ,  H04L25/02

    CPC classification number: H04J3/04 ,  H03K19/1737 ,  H04L25/0286

    Abstract: Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.

    Abstract translation: 本发明的示例性实施例涉及低功率电流模式逻辑（CML）无发射机架构。 发射机包括：主多路复用器，被配置为通过将从重定时器重新定时的并行主数据信号复用在并行输入数据信号之间的时间间隔和来自时钟分配器的多相时钟信号之间产生主数据信号，辅复用器被配置为生成后数据 通过复原从重定时器重新定时的并行后数据信号的多个输出驱动器，以及被配置为通过对主数据信号和后数据信号求和来产生串行数据信号的多个输出驱动器。

    Variable-precision distributed arithmetic multi-input multi-output equalizer for power-and-area-efficient optical dual-polarization quadrature phase-shift-keying system
    30.
    发明授权
    Variable-precision distributed arithmetic multi-input multi-output equalizer for power-and-area-efficient optical dual-polarization quadrature phase-shift-keying system 有权
    用于功率和面积效率的光学双极化正交相移键控系统的可变精度分布式算法多输入多输出均衡器

    公开(公告)号：US09036689B2

    公开(公告)日：2015-05-19

    申请号：US13740118

    申请日：2013-01-11

    Applicant: Korea Advanced Institute of Science and Technology

    Inventor： Hyeon Min Bae ,  Soon Won Kwon

    IPC: H03H7/30 ,  H04L25/03

    CPC classification number: H04L25/03891 ,  H04L25/03961 ,  H04L2025/03407

    Abstract: A variable-precision distributed arithmetic (VPDA) multi-input multi-output (MIMO) equalizer is presented to reduce the size and dynamic power of 112 Gbps dual-polarization quadrature phase-shift-keying (DP-QPSK) coherent optical communication receivers. The VPDA MIMO equalizer compensates for channel dispersion as well as various non-idealities of a time-interleaved successive approximation register (SAR) based analog-to-digital converter (ADC) simultaneously by using a least mean square (LMS) algorithm. As a result, area-hungry analog domain calibration circuits are not required. In addition, the VPDA MIMO equalizer achieves 45% dynamic power reduction over conventional finite impulse response (FIR) equalizers by utilizing the minimum required resolution for the equalization of each dispersed symbol.

    Abstract translation: 提出了一种可变精度分布算法（VPDA）多输入多输出（MIMO）均衡器，以减小112 Gbps双极化正交相移键控（DP-QPSK）相干光通信接收机的大小和动态功耗。 VPDA MIMO均衡器通过使用最小均方（LMS）算法同时补偿时间交错逐次逼近寄存器（SAR）的模数转换器（ADC）的信道色散以及各种非理想性。 因此，不需要占地面积的模拟域校准电路。 此外，VPDA MIMO均衡器通过利用每个分散符号的均衡的最小所需分辨率，实现了比传统有限脉冲响应（FIR）均衡器的45％动态功率降低。

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