公开(公告)号：US09743526B1

公开(公告)日：2017-08-22

申请号：US15040564

申请日：2016-02-10

Applicant: International Business Machines Corporation ,  SHINKO ELECTRIC INDUSTRIES CO., LTD

Inventor： Edmund Blackshear ,  Keiichi Hirabayashi ,  Yoichi Miyazawa ,  Brian W. Quinlan ,  Junji Sato

IPC: H05K1/18 ,  H05K3/32 ,  H05K3/40 ,  H05K1/11 ,  H05K3/46 ,  H05K3/00 ,  H05K1/02

CPC classification number: H05K1/185 ,  H05K1/0269 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/0055 ,  H05K3/32 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2203/1572 ,  H05K2203/16 ,  H05K2203/166

Abstract: A method of making a wiring board includes forming a first capacitor carrier layer with a first embedded chip capacitor, a first insulation layer disposed on an upper surface, a second insulation layer disposed on a lower surface, first upper and lower conductive vias in conductive contact with a first electrode, and second upper and lower conductive vias in conductive contact with a second electrode. The method also includes forming a second capacitor carrier layer similar to the first. The method further includes forming a bonded laminate comprising in sequence an upper insulation layer, the first capacitor carrier layer, a center insulation layer, the second capacitor carrier layer, and a lower insulation layer. The method also includes forming a through-hole through the laminate and forming a conductive coating within the through-hole to provide a conductive through-hole. A wiring board also includes the bonded laminate and the embedded capacitors.

公开(公告)号：US20170231094A1

公开(公告)日：2017-08-10

申请号：US15040564

申请日：2016-02-10

Applicant: International Business Machines Corporation ,  SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Edmund Blackshear ,  Keiichi Hirabayashi ,  Yoichi Miyazawa ,  Brian W. Quinlan ,  Junji Sato

IPC: H05K1/18 ,  H05K3/40 ,  H05K1/02 ,  H05K3/46 ,  H05K3/00 ,  H05K3/32 ,  H05K1/11

CPC classification number: H05K1/185 ,  H05K1/0269 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/0055 ,  H05K3/32 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2203/1572 ,  H05K2203/16 ,  H05K2203/166

Abstract: A method of making a wiring board includes forming a first capacitor carrier layer with a first embedded chip capacitor, a first insulation layer disposed on an upper surface, a second insulation layer disposed on a lower surface, first upper and lower conductive vias in conductive contact with a first electrode, and second upper and lower conductive vias in conductive contact with a second electrode. The method also includes forming a second capacitor carrier layer similar to the first. The method further includes forming a bonded laminate comprising in sequence an upper insulation layer, the first capacitor carrier layer, a center insulation layer, the second capacitor carrier layer, and a lower insulation layer. The method also includes forming a through-hole through the laminate and forming a conductive coating within the through-hole to provide a conductive through-hole. A wiring board also includes the bonded laminate and the embedded capacitors.

公开(公告)号：US09640492B1

公开(公告)日：2017-05-02

申请号：US14973130

申请日：2015-12-17

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Brian W. Quinlan

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/16 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/83862 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/45099

Abstract: A laminate includes a core, a buildup layer having a top and a bottom, the bottom contacting the core and a solder mask contacting the top, the solder mask including at least one warpage control region formed on a top surface of the solder mask.

公开(公告)号：US20220308564A1

公开(公告)日：2022-09-29

申请号：US17209574

申请日：2021-03-23

Applicant: International Business Machines Corporation

Inventor： Kirk D. Peterson ,  Steven Paul Ostrander ,  Stephanie E Allard ,  Charles L. Reynolds ,  Sungjun Chun ,  Daniel M. Dreps ,  Brian W. Quinlan ,  Sylvain Pharand ,  Jon Alfred Casey ,  David Edward Turnbull ,  Pascale Gagnon ,  Jean Labonte ,  Jean-Francois Bachand ,  Denis Blanchard

IPC: G05B19/418

Abstract: Multicomponent module assembly by identifying a failed site on a laminate comprising a plurality of sites, adding a machine discernible mark associated with the failed site, placing an electrically good element at a successful site; and providing an MCM comprising the laminate, and the electrically good element.

公开(公告)号：US10770385B2

公开(公告)日：2020-09-08

申请号：US16046653

申请日：2018-07-26

Applicant: International Business Machines Corporation

Inventor： Anson J. Call ,  Brian W. Quinlan ,  Krishna R. Tunga

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/10 ,  H01L23/053 ,  H01L23/367

Abstract: An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.

公开(公告)号：US10660209B2

公开(公告)日：2020-05-19

申请号：US15811852

申请日：2017-11-14

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Jean Audet ,  Francesco Preda

IPC: H05K1/18 ,  H01G4/33 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00 ,  H05K3/30 ,  H05K1/16 ,  H05K1/02

Abstract: A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.

公开(公告)号：US20200035593A1

公开(公告)日：2020-01-30

申请号：US16046653

申请日：2018-07-26

Applicant: International Business Machines Corporation

Inventor： Anson J. Call ,  Brian W. Quinlan ,  Krishna R. Tunga

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.

公开(公告)号：US20190172784A1

公开(公告)日：2019-06-06

申请号：US16269730

申请日：2019-02-07

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Jean Audet ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Brian R. Sundlof

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/50 ,  H01L23/00

Abstract: An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.

公开(公告)号：US20190150287A1

公开(公告)日：2019-05-16

申请号：US15811852

申请日：2017-11-14

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Jean Audet ,  Francesco Preda

IPC: H05K1/18 ,  H01G4/33 ,  H05K1/11 ,  H05K3/30 ,  H05K3/40 ,  H05K3/00

Abstract: A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.

公开(公告)号：US20190148283A1

公开(公告)日：2019-05-16

申请号：US16248013

申请日：2019-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Brian W. Quinlan

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.