公开(公告)号：US09136843B2

公开(公告)日：2015-09-15

申请号：US14447531

申请日：2014-07-30

Applicant: Industrial Technology Research Institute

Inventor： Pei-Ling Tseng ,  Keng-Li Su ,  Chih-Sheng Lin ,  Shyh-Shyuan Sheu

IPC: H03K19/00 ,  H03K19/003 ,  G01R31/28 ,  H01L21/66

CPC classification number: H03K19/003 ,  G01R31/28 ,  H01L22/22 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

Abstract: TSV repair circuit of a semiconductor device includes a first chip, a second chip, at least two TSV, at least two data path circuits and an output logic circuit. Each data path circuit comprises an input driving circuit, a TSV detection circuit, a memory device, a protection circuit and a power control circuit. The TSV detection circuit detects a TSV status, the memory device keeps the TSV status, the protection circuit determines whether to pull a first end of the TSV to a ground voltage according to the TSV status, and the power control circuit prevents a leakage current of a power voltage from flowing through a substrate.

Abstract translation: 半导体器件的TSV修复电路包括第一芯片，第二芯片，至少两个TSV，至少两个数据路径电路和输出逻辑电路。 每个数据路径电路包括输入驱动电路，TSV检测电路，存储器件，保护电路和功率控制电路。 TSV检测电路检测TSV状态，存储器件保持TSV状态，保护电路根据TSV状态确定是否将TSV的第一端拉至接地电压，并且功率控制电路防止漏电流 来自基板的电源电压。

公开(公告)号：US12265904B2

公开(公告)日：2025-04-01

申请号：US17131783

申请日：2020-12-23

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Shih-Chieh Chang ,  Shyh-Shyuan Sheu ,  Jian-Wei Su ,  Fu-Cheng Tsai

IPC: G06N3/063 ,  G06N3/045 ,  G06N3/0455

Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

公开(公告)号：US12260321B2

公开(公告)日：2025-03-25

申请号：US17385316

申请日：2021-07-26

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Fu-Cheng Tsai ,  Yi-Ching Kuo ,  Chih-Sheng Lin ,  Shyh-Shyuan Sheu ,  Tay-Jyi Lin ,  Shih-Chieh Chang

IPC: H03M1/12 ,  G06N3/04 ,  G06N3/063 ,  G11C27/02

Abstract: A data feature augmentation system and method for a low-precision neural network are provided. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample-and-hold circuit and a subtractor. The first sample-and-hold circuit is used for receiving an input signal and obtaining a first signal according to the input signal. The first signal is related to a first leakage rate of the first sample-and-hold circuit and the first signal is the signal generated by delaying the input signal by one time unit. The subtractor is used for performing subtraction on the input signal and the first signal to obtain a time difference signal. The input signal and the time difference signal are inputted to the low-precision neural network.

公开(公告)号：US10914618B2

公开(公告)日：2021-02-09

申请号：US15851609

申请日：2017-12-21

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Ya-Wen Yang ,  Kuan-Wei Chen ,  Shyh-Shyuan Sheu

IPC: G01D18/00 ,  G01D3/02

Abstract: A readout circuit for a sensor and a readout method thereof are provided. The readout circuit includes a reference circuit, a compensated circuit, and a signal processing circuit. The reference circuit provides a direct current (DC) signal. The compensated circuit is coupled to the reference circuit. The compensated circuit obtains an analog sensing signal of the sensor, obtains the DC signal from the reference circuit, and provides a compensated signal according to the analog sensing signal and the DC signal. The signal processing circuit is coupled to the compensated circuit. The signal processing circuit processes the compensated signal to convert the compensated signal into a digital sensing signal. The compensated circuit subtracts the DC signal from the analog sensing signal to provide the compensated signal.

公开(公告)号：US20210004678A1

公开(公告)日：2021-01-07

申请号：US16846427

申请日：2020-04-13

Applicant: Industrial Technology Research Institute

Inventor： Shih-Chieh Chang ,  Sih-Han Li ,  Shyh-Shyuan Sheu ,  Jian-Wei Su ,  Heng-Yuan Lee

IPC: G06N3/08 ,  G11C11/54 ,  G06N3/04

Abstract: A neural circuit is provided. The neural circuit includes a neural array. The neural array includes a plurality of semiconductor components. Each of the semiconductor components stores a weighting value to generate a corresponding output current or a corresponding equivalent resistance. The neural array receives a plurality of input signals to control the semiconductor components in the neural array and respectively generates the output currents or changes the equivalent resistances. Since the semiconductor components are coupled to each other, output of the neural array may generate a summation current or a summation equivalent resistance related to the input signals and a weighting condition, so that a computing result exhibits high performance.

公开(公告)号：US08872543B2

公开(公告)日：2014-10-28

申请号：US13872168

申请日：2013-04-29

Applicant: Industrial Technology Research Institute

Inventor： Wen-Pin Lin ,  Chih-He Lin ,  Shyh-Shyuan Sheu ,  Hsin-Chi Lai

IPC: H03K19/173 ,  G06F7/38 ,  H03K19/177

CPC classification number: H03K19/1776

Abstract: A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit.

Abstract translation: 提供了可配置逻辑块（CLB）和CLB的操作方法。 CLB包括存储单元和选择电路。 存储单元包括第一电阻性非易失性存储器（RNVM）元件和第二RNVM元件。 第一和第二RNVM元件的顶部电极（TE）耦合到存储器单元的输出端子。 第一和第二RNVM元件的底部电极（BE）分别耦合到存储器单元的第一偏置端子和第二偏置端子。 选择电路根据输入逻辑值选择一个存储器单元，并根据所选存储器单元的输出逻辑值确定CLB的输出逻辑值。

公开(公告)号：US20140210514A1

公开(公告)日：2014-07-31

申请号：US13872168

申请日：2013-04-29

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Wen-Pin Lin ,  Chih-He Lin ,  Shyh-Shyuan Sheu ,  Hsin-Chi Lai

IPC: H03K19/177

CPC classification number: H03K19/1776

Abstract: A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit.

Abstract translation: 提供了可配置逻辑块（CLB）和CLB的操作方法。 CLB包括存储单元和选择电路。 存储单元包括第一电阻性非易失性存储器（RNVM）元件和第二RNVM元件。 第一和第二RNVM元件的顶部电极（TE）耦合到存储器单元的输出端子。 第一和第二RNVM元件的底部电极（BE）分别耦合到存储器单元的第一偏置端子和第二偏置端子。 选择电路根据输入逻辑值选择一个存储器单元，并根据所选存储器单元的输出逻辑值确定CLB的输出逻辑值。