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公开(公告)号：US20210357212A1
公开(公告)日：2021-11-18
申请号：US17327957
申请日：2021-05-24
Applicant: Google LLC
Inventor： William Lacy , Gregory Michael Thorson , Christopher Aaron Clark , Norman Paul Jouppi , Thomas Norrie , Andrew Everett Phelps
Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.
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公开(公告)号：US20210255976A1
公开(公告)日：2021-08-19
申请号：US16838796
申请日：2020-04-02
Applicant: Google LLC
IPC: G06F13/28
Abstract: DMA architectures capable of performing multi-level multi-striding and determining multiple memory addresses in parallel are described. In one aspect, a DMA system includes one or more hardware DMA threads. Each DMA thread includes a request generator configured to generate, during each parallel memory address computation cycle, m memory addresses for a multi-dimensional tensor in parallel and, for each memory address, a respective request for a memory system to perform a memory operation. The request generator includes m memory address units that each include a step tracker configured to generate, for each dimension of the tensor, a respective step index value for the dimension and, based on the respective step index value, a respective stride offset value for the dimension. Each memory address unit includes a memory address computation element configured to generate a memory address for a tensor element and transmit the request to perform the memory operation.
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公开(公告)号：US11049016B2
公开(公告)日：2021-06-29
申请号：US16824411
申请日：2020-03-19
Applicant: Google LLC
Inventor： Jonathan Ross , Norman Paul Jouppi , Andrew Everett Phelps , Reginald Clifford Young , Thomas Norrie , Gregory Michael Thorson , Dan Luu
Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.
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公开(公告)号：US10324817B2
公开(公告)日：2019-06-18
申请号：US15875160
申请日：2018-01-19
Applicant: Google LLC
Inventor： Thomas Norrie , Naveen Kumar
Abstract: A computer-implemented method executed by one or more processors, the method includes monitoring execution of program code executed by a first processor component; and monitoring execution of program code executed by a second processor component. A computing system stores data identifying hardware events in a memory buffer. The stored events occur across processor units that include at least the first and second processor components. The hardware events each include an event time stamp and metadata characterizing the event. The system generates a data structure identifying the hardware events. The data structure arranges the events in a time ordered sequence and associates events with at least the first or second processor components. The system stores the data structure in a memory bank of a host device and uses the data structure to analyze performance of the program code executed by the first or second processor components.
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公开(公告)号：US11650895B2
公开(公告)日：2023-05-16
申请号：US17240838
申请日：2021-04-26
Applicant: Google LLC
Inventor： Thomas Norrie , Naveen Kumar
CPC classification number: G06F11/302 , G06F9/542 , G06F11/3072 , G06F11/3075 , G06F11/3476 , G06F11/3495 , G06F11/3636 , G06F16/489 , G06F2201/86 , G06F2201/865
Abstract: A computer-implemented method executed by one or more processors, the method includes monitoring execution of program code executed by a first processor component; and monitoring execution of program code executed by a second processor component. A computing system stores data identifying hardware events in a memory buffer. The stored events occur across processor units that include at least the first and second processor components. The hardware events each include an event time stamp and metadata characterizing the event. The system generates a data structure identifying the hardware events. The data structure arranges the events in a time ordered sequence and associates events with at least the first or second processor components. The system stores the data structure in a memory bank of a host device and uses the data structure to analyze performance of the program code executed by the first or second processor components.
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Patent Agency Ranking
公开(公告)号：US20220261622A1
公开(公告)日：2022-08-18
申请号：US17694598
申请日：2022-03-14
Applicant: Google LLC
Inventor： Thomas Norrie , Olivier Temam , Andrew Everett Phelps , Norman Paul Jouppi
Abstract: Methods, systems, and apparatus including a special purpose hardware chip for training neural networks are described. The special-purpose hardware chip may include a scalar processor configured to control computational operation of the special-purpose hardware chip. The chip may also include a vector processor configured to have a 2-dimensional array of vector processing units which all execute the same instruction in a single instruction, multiple-data manner and communicate with each other through load and store instructions of the vector processor. The chip may additionally include a matrix multiply unit that is coupled to the vector processor configured to multiply at least one two-dimensional matrix with a second one-dimensional vector or two-dimensional matrix in order to obtain a multiplication result.
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公开(公告)号：US20220156071A1
公开(公告)日：2022-05-19
申请号：US17530869
申请日：2021-11-19
Applicant: Google LLC
Inventor： Thomas Norrie , Gurushankar Rajamani , Andrew Everett Phelps , Matthew Leever Hedlund , Norman Paul Jouppi
Abstract: Methods, systems, and apparatus, including computer-readable media, are described for performing vector reductions using a shared scratchpad memory of a hardware circuit having processor cores that communicate with the shared memory. For each of the processor cores, a respective vector of values is generated based on computations performed at the processor core. The shared memory receives the respective vectors of values from respective resources of the processor cores using a direct memory access (DMA) data path of the shared memory. The shared memory performs an accumulation operation on the respective vectors of values using an operator unit coupled to the shared memory. The operator unit is configured to accumulate values based on arithmetic operations encoded at the operator unit. A result vector is generated based on performing the accumulation operation using the respective vectors of values.
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公开(公告)号：US11314674B2
公开(公告)日：2022-04-26
申请号：US16838796
申请日：2020-04-02
Applicant: Google LLC
Abstract: DMA architectures capable of performing multi-level multi-striding and determining multiple memory addresses in parallel are described. In one aspect, a DMA system includes one or more hardware DMA threads. Each DMA thread includes a request generator configured to generate, during each parallel memory address computation cycle, m memory addresses for a multi-dimensional tensor in parallel and, for each memory address, a respective request for a memory system to perform a memory operation. The request generator includes m memory address units that each include a step tracker configured to generate, for each dimension of the tensor, a respective step index value for the dimension and, based on the respective step index value, a respective stride offset value for the dimension. Each memory address unit includes a memory address computation element configured to generate a memory address for a tensor element and transmit the request to perform the memory operation.
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公开(公告)号：US20210248052A1
公开(公告)日：2021-08-12
申请号：US17240838
申请日：2021-04-26
Applicant: Google LLC
Inventor： Thomas Norrie , Naveen Kumar
Abstract: A computer-implemented method executed by one or more processors, the method includes monitoring execution of program code executed by a first processor component; and monitoring execution of program code executed by a second processor component. A computing system stores data identifying hardware events in a memory buffer. The stored events occur across processor units that include at least the first and second processor components. The hardware events each include an event time stamp and metadata characterizing the event. The system generates a data structure identifying the hardware events. The data structure arranges the events in a time ordered sequence and associates events with at least the first or second processor components. The system stores the data structure in a memory bank of a host device and uses the data structure to analyze performance of the program code executed by the first or second processor components.
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公开(公告)号：US10990494B2
公开(公告)日：2021-04-27
申请号：US16665355
申请日：2019-10-28
Applicant: Google LLC
Inventor： Thomas Norrie , Naveen Kumar
Abstract: A computer-implemented method executed by one or more processors, the method includes monitoring execution of program code executed by a first processor component; and monitoring execution of program code executed by a second processor component. A computing system stores data identifying hardware events in a memory buffer. The stored events occur across processor units that include at least the first and second processor components. The hardware events each include an event time stamp and metadata characterizing the event. The system generates a data structure identifying the hardware events. The data structure arranges the events in a time ordered sequence and associates events with at least the first or second processor components. The system stores the data structure in a memory bank of a host device and uses the data structure to analyze performance of the program code executed by the first or second processor components.
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