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    ENCODER AND OPERATION METHOD THEREOF
    25.
    发明申请
    ENCODER AND OPERATION METHOD THEREOF 有权

    公开(公告)号：US20230125421A1

    公开(公告)日：2023-04-27

    申请号：US17893815

    申请日：2022-08-23

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Tae Wook KANG ,  Sung Eun KIM ,  Kyung Jin BYUN ,  Kwang IL OH ,  Jae-Jin LEE

    IPC: G06N3/04 ,  G06N10/20

    Abstract: Disclosed is operation method of an encoder that receives a continuous time-series signal and respectively transmits first to N-th input signals to first to N-th input neuron circuits of spike neural network circuit. The method of operating the encoder includes receiving the continuous time-series signal, generating a plurality of discrete quantum signals by sampling and quantizing the continuous time-series signal, selecting first to N-th discrete quantum signals among the plurality of discrete quantum signals, matching the selected first to N-th discrete quantum signals with the first to N-th input neuron circuits, respectively, identifying discrete quantum signals, each of which has a quantum level different from a quantum level of a previous discrete quantum signal, from among the second to N-th discrete quantum signals, and activating the input signals to be transmitted to the input neuron circuits corresponding to the identified discrete quantum signals and the first discrete quantum signal.

    LOW POWER SYSTEM ON CHIP
    26.
    发明申请
    LOW POWER SYSTEM ON CHIP 有权

    公开(公告)号：US20220413544A1

    公开(公告)日：2022-12-29

    申请号：US17847636

    申请日：2022-06-23

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kyuseung HAN ,  Tae Wook KANG ,  Sung Eun KIM ,  Hyuk KIM ,  Hyung-IL PARK ,  Kwang IL OH ,  Jae-Jin LEE

    IPC: G06F1/10 ,  G06F15/78

    Abstract: A low power system on chip for supporting partial clock gating is provided. The system on chip includes a network on chip including a first CG-network interface module, a second CG-network interface module, and a clock gating control module, a first IP block that communicates through the first CG-network interface module, and a second IP block that communicates through the second CG-network interface module. The clock gating control module receives a clock gating request from the first IP block, outputs a communication control signal to the second CG-network interface module in response to the received clock gating request, and performs a clock gating operation for a clock signal in response to the received clock gating request to selectively deliver the clock signal to the second IP block.

    SPIKING NEURAL NETWORK CIRCUIT
    29.
    发明申请
    SPIKING NEURAL NETWORK CIRCUIT 有权

    公开(公告)号：US20220156556A1

    公开(公告)日：2022-05-19

    申请号：US17446685

    申请日：2021-09-01

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kwang IL OH ,  Tae Wook KANG ,  Sung Eun KIM ,  Hyuk KIM ,  Hyung-IL PARK ,  Jae-Jin LEE

    IPC: G06N3/04 ,  G06N3/063 ,  H03K19/20

    Abstract: Disclosed is a spiking neural network circuit, which includes an axon circuit that generates an input spike signal, a first synapse zone and a second synapse zone each including one or more synapses, wherein each of the synapses is configured to perform an operation based on the input spike signal and each weight, and a neuron circuit that generates an output spike signal based on operation results of the synapses. The input spike signal is transferred to the first synapse zone and the second synapse zone through a tree structure, and each of branch nodes of the tree structure includes a driving buffer.

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