公开(公告)号：US09461073B2

公开(公告)日：2016-10-04

申请号：US14429870

申请日：2014-06-05

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhiqiang Xu ,  Heecheol Kim ,  Chao Xu

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1337 ,  G02F1/1343

CPC classification number: H01L27/124 ,  G02F1/133707 ,  G02F1/134363 ,  G02F1/1368 ,  G02F2001/134372 ,  H01L27/12 ,  H01L27/1259

Abstract: The embodiments of the invention provide an array substrate, a method for manufacturing the same and a display device, relate to the field of display technology, and can reduce the color cast phenomenon of the display device, and improve the display effect. The array substrate comprises a plurality of pixel units which are arranged in an array, each of the pixel units comprises a plurality of sub-pixel units, the width of each of the sub-pixel units is equal, each of the sub-pixel units corresponds to one first electrode, the first electrode comprises a plurality of strip-shaped structures which are arranged at an equal interval, and intervals of the strip-shaped structures of the first electrodes corresponding to different sub-pixel units in each of the pixel units are not completely equal; any of the sub-pixel units meets Q·W+(Q−1)D

Abstract translation: 本发明的实施例提供阵列基板，其制造方法和显示装置，涉及显示技术领域，并且可以减少显示装置的着色现象​​，并提高显示效果。 阵列基板包括以阵列布置的多个像素单元，每个像素单元包括多个子像素单元，每个子像素单元的宽度相等，每个子像素单元 对应于一个第一电极，第一电极包括以等间隔布置的多个条形结构，并且第一电极的条形结构的间隔对应于每个像素单元中的不同子像素单元 不完全平等 任何子像素单元满足Q·W +（Q-1）D

公开(公告)号：US09323111B2

公开(公告)日：2016-04-26

申请号：US14105379

申请日：2013-12-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yoon-Sung Um ,  Hyun-Sic Choi ,  Zhiqiang Xu ,  Hui Li

IPC: G02F1/1343 ,  G02F1/136 ,  G02F1/1362

CPC classification number: G02F1/1343 ,  G02F1/134309 ,  G02F1/136 ,  G02F1/136286 ,  G02F2001/134318 ,  G02F2001/13606 ,  G02F2001/136218 ,  Y10T29/49117

Abstract: The present invention provides an array substrate, its manufacturing method, and a display device. The array substrate comprises a plurality of grid lines a plurality of data lines, and pixel regions defined by every two adjacent grid Fines and every two adjacent data lines. The pixel region is provided with a common electrode, a pixel electrode and a thin film transistor. The common electrode includes a first common electrode and a second common electrode which are powered independently. A projection of the first common electrode onto a layer where the data lines are located covers the data line, and a projection of the second common electrode onto a layer where the pixel electrode is located falls on the pixel electrode.

Abstract translation: 本发明提供阵列基板，其制造方法和显示装置。 阵列基板包括多个网格线，多条数据线，以及由每两个相邻网格细分和每两个相邻数据线定义的像素区域。 像素区域设置有公共电极，像素电极和薄膜晶体管。 公共电极包括独立供电的第一公共电极和第二公共电极。 第一公共电极到数据线所在的层的投影覆盖数据线，并且第二公共电极在像素电极所在的层上的投影落在像素电极上。

公开(公告)号：US09105248B2

公开(公告)日：2015-08-11

申请号：US14071823

申请日：2013-11-05

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yoon-Sung Um ,  Hyun-Sic Choi ,  Zhiqiang Xu ,  Hui Li

IPC: G09G3/36

CPC classification number: G09G3/3614 ,  G09G2300/0426 ,  G09G2320/0233

Abstract: Embodiments of the present disclosure provide an array substrate comprising a plurality of gate lines, a plurality of data lines, and pixel regions each of which is defined by intersecting one gate line and two neighboring data lines among the plurality of gate lines and the plurality of data lines wherein two thin film transistors (TFTs) are formed at the intersections between the gate line and the two neighboring data lines in each pixel region, a first pixel electrode and a second pixel electrode are alternately arranged in each pixel region. A first thin film transistor of the two thin film transistors is coupled to the first pixel electrode, a second thin film transistor of the two thin film transistors is coupled to the second pixel electrode. The two neighboring data lines participating in defining a pixel region comprise a first data line coupling to the first thin film transistor and a second data line coupling to the second thin film transistor. Voltages having the same absolute value and opposite polarities are applied to the first pixel electrode and the second pixel electrode respectively via the first thin film transistor and the second thin film transistor.

Abstract translation: 本公开的实施例提供了一种阵列基板，其包括多条栅极线，多条数据线和像素区域，每条栅极线路与多条栅极线路中的一条栅极线和两条相邻的数据线相交， 数据线，其中在每个像素区域中的栅极线和两个相邻数据线之间的交点处形成两个薄膜晶体管（TFT），第一像素电极和第二像素电极在每个像素区域中交替布置。 两个薄膜晶体管的第一薄膜晶体管耦合到第一像素电极，两个薄膜晶体管的第二薄膜晶体管耦合到第二像素电极。 参与定义像素区域的两个相邻数据线包括耦合到第一薄膜晶体管的第一数据线和耦合到第二薄膜晶体管的第二数据线。 具有相同绝对值和相反极性的电压分别经由第一薄膜晶体管和第二薄膜晶体管施加到第一像素电极和第二像素电极。

公开(公告)号：US20140049740A1

公开(公告)日：2014-02-20

申请号：US13954038

申请日：2013-07-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhiqiang Xu ,  Hyunsic Chol ,  Yoonsung Um ,  Hui Li

IPC: G02F1/1343

CPC classification number: G02F1/134336 ,  G02F1/134363 ,  G02F1/13624

Abstract: Embodiments of the present invention disclose a liquid crystal display device, comprising: a first substrate, including a base substrate, and gate lines and data lines, formed on the base substrate and crossing each other to define a plurality of pixel structures; a second substrate, cell-assembled with the first substrate to form a liquid crystal cell; and a liquid crystal layer, filled between the first substrate and the second substrate, wherein each of the plurality of pixel structures comprises: the base substrate; a common electrode, formed on the base substrate; a first insulating layer, formed on the common electrode; a plurality of strip-shaped pixel electrodes, formed on the first insulating layer, wherein the plurality of strip-shaped pixel electrodes include a plurality of positive electrodes and negative electrodes which are disposed alternately.

Abstract translation: 本发明的实施例公开了一种液晶显示装置，包括：形成在基底基板上并彼此交叉以限定多个像素结构的包括基底基板的第一基板和栅极线和数据线; 第二基板，与第一基板电池组装以形成液晶单元; 以及填充在所述第一基板和所述第二基板之间的液晶层，其中所述多个像素结构中的每一个包括：所述基底; 形成在基底基板上的公共电极; 形成在公共电极上的第一绝缘层; 形成在所述第一绝缘层上的多个带状像素电极，其中所述多个条形像素电极包括交替设置的多个正电极和负电极。

公开(公告)号：US20250069554A1

公开(公告)日：2025-02-27

申请号：US18687937

申请日：2023-08-22

Applicant: Beijing BOE Technology Development Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Weixing Liu ,  Wanpeng Teng ,  Zhiqiang Xu ,  Chunfang Zhang ,  Meirong Lu ,  Jintao Peng ,  Xinxing Wang ,  Huanhuan Wang

IPC: G09G3/3266 ,  G09G3/3233 ,  G11C19/28

Abstract: A shift register, a driving circuit, a driving method and a display device are provided. The shift register includes: an input circuit configured to provide a first voltage or a second voltage to a first node and a light-emitting control signal terminal under a control of a first input signal and a second input signal; a processing circuit configured to provide the first voltage or the second voltage to a second node under a control of the first input signal and a potential of the first node; and an output circuit configured to provide the first voltage or the second voltage to a first output scanning signal terminal under control of a first clock signal and the potential of the first node, and provide the first voltage or the second voltage to a second output scanning signal terminal under a control of a potential of the first output scanning signal terminal.

公开(公告)号：US12219807B2

公开(公告)日：2025-02-04

申请号：US17330704

申请日：2021-05-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wei Qin ,  Zhiqiang Xu ,  Weixing Liu ,  Wanpeng Teng ,  Chunfang Zhang

IPC: H10K59/121 ,  H10K59/65

Abstract: The present disclosure relates to a display panel and a terminal device. The display panel includes a display region. At least a part of the display region is a transparent region. The transparent region has a plurality of pixel rows distributed along a column direction, and each of the plurality of pixel rows includes pixels and transparent portions arranged in a row direction. The pixel rows include first pixel rows and second pixel rows, transparent portions each arranged between two adjacent pixels in each of the first pixel rows are first transparent portions, and transparent portions each arranged between two adjacent pixels in each of the second pixel rows are second transparent portions. A width of each of the first transparent portions in the row direction is greater than a width of each of the second transparent portions in the row direction.

公开(公告)号：US20240268149A1

公开(公告)日：2024-08-08

申请号：US18041070

申请日：2022-03-22

Applicant: BOE Technology Group Co., Ltd.

Inventor： Weixing Liu ,  Wanpeng Teng ,  Tieshi Wang ,  Chunfang Zhang ,  Kai Guo ,  Xiaolong Li ,  Zhiqiang Xu

IPC: H10K59/121 ,  G09G3/3258 ,  H10K59/131 ,  H10K59/38

CPC classification number: H10K59/1213 ,  G09G3/3258 ,  H10K59/1216 ,  H10K59/131 ,  H10K59/38 ,  G09G2300/0426 ,  G09G2300/0852

Abstract: A light emitting substrate is provided. The light emitting substrate includes a plurality of subpixels. A respective subpixel of the plurality of subpixels includes n1 number of main light emitting elements; n1 number of main pixel driving circuits configured to drive light emission in the n1 number of main light emitting elements; n2 number of auxiliary light emitting elements; n2 number of auxiliary pixel driving circuits configured to drive light emission in the n2 number of auxiliary light emitting elements; n1≥1, and n2≥1. A respective main pixel driving circuit of the n1 number of main pixel driving circuits includes a first driving transistor. A respective auxiliary pixel driving circuit of the n2 number of auxiliary pixel driving circuits includes a second driving transistor. Threshold voltage levels of the first driving transistor and the second driving transistor are substantially the same

公开(公告)号：US20240242688A1

公开(公告)日：2024-07-18

申请号：US18004901

申请日：2022-01-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xiaolong Li ,  Kuanjun Peng ,  Kai Guo ,  Wanpeng Teng ,  Chunfang Zhang ,  Weixing Liu ,  Zhiqiang Xu ,  Tieshi Wang ,  Feihu Zhou

IPC: G09G3/36

CPC classification number: G09G3/3648 ,  G09G2320/0209 ,  G09G2354/00 ,  G09G2360/16

Abstract: A display method is provided. The display method includes providing a display panel having a plurality of subpixels, a respective subpixel of the plurality of subpixels including a first area, n1 number of second areas, and n2 number of third areas, the first area being between the n1 number of second areas and the n2 number of third areas, n1≥1, and n2≥1; for displaying a first frame of image, controlling light emission of the respective subpixel to be limited in the first area, m1 number of the n1 number of second areas, and m2 number of the n2 number of third areas; and for displaying a second frame of image, controlling light emission of the respective subpixel to be limited in the first area, ml′ number of the n1 number of second areas, and m2′ number of the n2 number of third areas.

公开(公告)号：US11837133B2

公开(公告)日：2023-12-05

申请号：US17609504

申请日：2021-01-28

Applicant: BOE Technology Group Co., Ltd.

Inventor： Weixing Liu ,  Wei Qin ,  Kuanjun Peng ,  Tieshi Wang ,  Chunfang Zhang ,  Hui Zhang ,  Changfeng Li ,  Shunhang Zhang ,  Kai Hou ,  Hongrun Wang ,  Liwei Liu ,  Yunsik Im ,  Wanpeng Teng ,  Xiaolong Li ,  Kai Guo ,  Zhiqiang Xu

IPC: G09G3/20 ,  G11C19/28

CPC classification number: G09G3/20 ,  G11C19/287 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/08

Abstract: The present disclosure provides a gate driving circuit, a method of driving a gate driving circuit, and a display panel. The gate driving circuit includes a plurality of driving units connected in cascade. Each driving unit includes: N shift register units; and a mode control circuit connected to the N shift register units, wherein the mode control circuit is configured to receive a control signal for the driving unit, and connect the N shift register units in one of a plurality of resolution modes under the control of the control signal.

公开(公告)号：US11651737B2

公开(公告)日：2023-05-16

申请号：US17726875

申请日：2022-04-22

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Tieshi Wang ,  Xueling Gao ,  Zhiqiang Xu ,  Chengchung Yang ,  Haoran Liu

IPC: G09G3/3258 ,  G09G3/3233 ,  G09G3/3266

CPC classification number: G09G3/3258 ,  G09G3/3233 ,  G09G3/3266

Abstract: A circuit for driving a pixel includes a driving transistor having a first end connected to a first node, a control end connected to a second node, and a second end connected to a third node; a writing circuit connected to a first scanning signal and the first node and configured to transmit a data signal to the first node; a reset circuit connected to a second scanning signal and configured to transmit a reference signal to the second node; a compensation circuit connected to a compensation control signal and configured to put through a connection between the second end and the control end of the driving transistor in response to the compensation control signal, wherein the compensation control signal is different from the first scanning signal and the second scanning signal; and an energy storage circuit connected between a first power end and the second node.