Mass transfer method and system for micro light emitting diodes

    公开(公告)号:US11437265B2

    公开(公告)日:2022-09-06

    申请号:US16770655

    申请日:2019-06-13

    Abstract: The present disclosure discloses a mass transfer method and system for micro light emitting diodes, wherein the mass transfer method includes: providing a component substrate on which a plurality of micro light emitting diodes are formed; picking up the micro light emitting diodes on the component substrate at least once by a plurality of bonding structures on a first medium load substrate, and transferring micro light emitting diodes picked up every time to a second medium load substrate; and transferring the micro light emitting diodes on the second medium load substrate into corresponding sub-pixels on a target substrate at one time, wherein one of the micro light emitting diodes on the second medium load substrate corresponds to one of the sub-pixels on the target substrate.

    Array substrate, display device, and method for manufacturing same

    公开(公告)号:US11316003B2

    公开(公告)日:2022-04-26

    申请号:US16959010

    申请日:2020-02-25

    Abstract: Disclosed are an array substrate, and a display device, and a method for manufacturing the same. The array substrate includes: a base substrate, and a thin film transistor, a planarization pattern, a bonding pattern, and a conductive structure that are disposed on the base substrate. The thin film transistor, the planarization pattern, and the bonding pattern are laminated in a direction going distally from the base substrate. The planarization pattern is provided with a via and a groove, the conductive structure is disposed in the via, wherein the bonding pattern is conductive and is electrically connected to the thin film transistor by the conductive structure, an orthographic projection of the bonding pattern on the base substrate falls outside an orthographic projection of the groove on the base substrate, and the groove is configured to accommodate an adhesive.

    Circuit backplane of display panel, method for manufacturing the circuit backplane, and display panel

    公开(公告)号:US11257852B2

    公开(公告)日:2022-02-22

    申请号:US16966146

    申请日:2019-12-25

    Abstract: A circuit backplane of a display panel, a method for manufacturing the same, and a display panel are provided. The circuit backplane includes a substrate and a plurality of circuit regions on the substrate. Each of the plurality of circuit regions includes a cathode soldered electrode, an anode soldered electrode, and a flow blocking island that are on the substrate. The flow blocking island is between the cathode soldered electrode and the anode soldered electrode, and in a thickness direction of the circuit backplane, a height of the flow blocking island is greater than each of a height of the cathode soldered electrode and a height of the anode soldered electrode.

    Micro-LED display panel with stress releasing structure and method for fabricating the same

    公开(公告)号:US11244966B2

    公开(公告)日:2022-02-08

    申请号:US16682395

    申请日:2019-11-13

    Abstract: A micro LED display panel and a method for fabricating the same are disclosed, and the micro LED display panel includes a TFT back panel, and a micro LED fixed on the TFT back panel, wherein the TFT back panel includes a substrate, and a first insulation layer and a second insulation layer stacked over the substrate in that order, wherein the first insulation layer includes a groove filled with the second insulation layer, and a normal projection of the groove onto the substrate does not overlap with a normal projection of a TFT area in the TFT back panel onto the substrate, wherein the rigidity of the second insulation layer is lower than the rigidity of the first insulation layer.

    Array substrate and fabrication method thereof, and electronic apparatus

    公开(公告)号:US11239221B2

    公开(公告)日:2022-02-01

    申请号:US16631016

    申请日:2018-11-02

    Inventor: Haixu Li

    Abstract: An array substrate and a fabrication method thereof, and an electronic apparatus are disclosed. The array substrate includes a base substrate, a thin film transistor, a first connection electrode and a first insulation layer. The thin film transistor is on the base substrate and including a first electrode and a second electrode; the first connection electrode in a layer different from the first electrode and electrically connected with the first electrode; and the first insulation layer covering at least a portion of the first connection electrode; an area of an orthographic projection of the first connection electrode on the base substrate is larger than an area of an orthographic projection of the first electrode on the base substrate, and the first insulation layer is made from an organic insulation material.

    Array Substrate And Fabrication Method Thereof, And Electronic Apparatus

    公开(公告)号:US20210066267A1

    公开(公告)日:2021-03-04

    申请号:US16631016

    申请日:2018-11-02

    Inventor: Haixu Li

    Abstract: An array substrate and a fabrication method thereof, and an electronic apparatus are disclosed. The array substrate includes a base substrate, a thin film transistor, a first connection electrode and a first insulation layer. The thin film transistor is on the base substrate and including a first electrode and a second electrode; the first connection electrode in a layer different from the first electrode and electrically connected with the first electrode; and the first insulation layer covering at least a portion of the first connection electrode; an area of an orthographic projection of the first connection electrode on the base substrate is larger than an area of an orthographic projection of the first electrode on the base substrate, and the first insulation layer is made from an organic insulation material.

    WIRING STRUCTURE, PREPARATION METHOD THEREOF, AND DISPLAY DEVICE

    公开(公告)号:US20210064104A1

    公开(公告)日:2021-03-04

    申请号:US16643919

    申请日:2019-08-14

    Abstract: The present disclosure provides a wiring structure, a preparation method thereof, and a display device. The wiring structure includes a substrate; a pre-arranged layer located on the substrate; and an electrode wiring covering the pre-arranged layer; wherein in the direction perpendicular to an extending direction of the electrode wiring and parallel to a plane on which the substrate is located, an orthographic projection of the pre-arranged layer on the substrate is located within an orthographic projection of the electrode wiring on the substrate, and a side surface of the pre-arranged layer is inclined relative to the plane on which the substrate is located.

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