公开(公告)号：US10128337B2

公开(公告)日：2018-11-13

申请号：US15173234

申请日：2016-06-03

Applicant: Applied Materials, Inc.

Inventor： Jie Zhou ,  Zhong Qiang Hua ,  Chentsau Ying ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/308 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/67 ,  H01L21/677

Abstract: Methods for forming fin structures with desired profile and dimensions for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. The methods include a structure reshaping process to reshape a shaped structure, such as a diamond like structure formed on a fin structure. In one embodiment, a method for forming a structure on a substrate includes performing an epitaxial deposition process to form a shaped structure on a fin structure disposed on a substrate, performing a mask layer deposition process to form a mask layer having a first width on the shaped structure, and performing a mask trimming process to trim the mask layer from the first width from a second width.

公开(公告)号：US09865484B1

公开(公告)日：2018-01-09

申请号：US15197060

申请日：2016-06-29

Applicant: Applied Materials, Inc.

Inventor： Bhargav Citla ,  Chentsau Ying ,  Srinivas Nemani ,  Viachslav Babayan ,  Michael Stowell

IPC: H01L21/67 ,  H01L21/683 ,  H01L21/687 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/67069 ,  H01J37/32146 ,  H01J37/32706 ,  H01J2237/334 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/6831 ,  H01L21/6833 ,  H01L21/68735

Abstract: Semiconductor systems and methods may include methods of performing selective etches that include modifying a material on a semiconductor substrate. The substrate may have at least two exposed materials on a surface of the semiconductor substrate. The methods may include forming a low-power plasma within a processing chamber housing the semiconductor substrate. The low-power plasma may be a radio-frequency (“RF”) plasma, which may be at least partially formed by an RF bias power operating between about 10 W and about 100 W in embodiments. The RF bias power may also be pulsed at a frequency below about 5,000 Hz. The methods may also include etching one of the at least two exposed materials on the surface of the semiconductor substrate at a higher etch rate than a second of the at least two exposed materials on the surface of the semiconductor substrate.

公开(公告)号：US20180005850A1

公开(公告)日：2018-01-04

申请号：US15197060

申请日：2016-06-29

Applicant: Applied Materials, Inc.

Inventor： Bhargav Citla ,  Chentsau Ying ,  Srinivas Nemani ,  Viachslav Babayan ,  Michael Stowell

IPC: H01L21/67 ,  H01L21/683 ,  H01L21/3115 ,  H01L21/687 ,  H01L21/311

CPC classification number: H01L21/67069 ,  H01J37/32146 ,  H01J37/32706 ,  H01J2237/334 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/6831 ,  H01L21/6833 ,  H01L21/68735

Abstract: Semiconductor systems and methods may include methods of performing selective etches that include modifying a material on a semiconductor substrate. The substrate may have at least two exposed materials on a surface of the semiconductor substrate. The methods may include forming a low-power plasma within a processing chamber housing the semiconductor substrate. The low-power plasma may be a radio-frequency (“RF”) plasma, which may be at least partially formed by an RF bias power operating between about 10 W and about 100 W in embodiments. The RF bias power may also be pulsed at a frequency below about 5,000 Hz. The methods may also include etching one of the at least two exposed materials on the surface of the semiconductor substrate at a higher etch rate than a second of the at least two exposed materials on the surface of the semiconductor substrate.

公开(公告)号：US09640385B2

公开(公告)日：2017-05-02

申请号：US15000273

申请日：2016-01-19

Applicant: Applied Materials, Inc.

Inventor： Bhargav Citla ,  Chentsau Ying ,  Srinivas D. Nemani

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/3213

CPC classification number: H01L21/02071 ,  H01L21/28035 ,  H01L21/32137

Abstract: The present disclosure provides methods for removing gate electrode residuals from a gate structure after a gate electrode patterning process. In one example, a method for forming high aspect ratio features in a gate electrode layer in a gate structure includes performing an surface treatment process on gate electrode residuals remaining on a gate structure disposed on a substrate, selectively forming a treated residual in the gate structure on the substrate with some untreated regions nearby in the gate structure, and performing a remote plasma residual removal process to remove the treated residual from the substrate.

公开(公告)号：US09190290B2

公开(公告)日：2015-11-17

申请号：US14231180

申请日：2014-03-31

Applicant: Applied Materials, Inc.

Inventor： Jun Xue ,  Chentsau Ying ,  Srinivas D. Nemani

IPC: H01L37/00 ,  H01L21/311 ,  H01L21/3065

CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01L21/3065 ,  H01L21/32137 ,  H01L29/66545

Abstract: A method of selectively dry etching silicon from patterned heterogeneous structures is described. The method optionally includes a plasma process prior to a remote plasma etch. The plasma process may use a biased plasma to treat some crystalline silicon (e.g. polysilicon or single crystal silicon) to form amorphous silicon. Subsequently, a remote plasma is formed using a hydrogen-containing precursor to form plasma effluents. The plasma effluents are passed into the substrate processing region to etch the amorphous silicon from the patterned substrate. By implementing biased plasma processes, the normally isotropic etch may be transformed into a directional (anisotropic) etch despite the remote nature of the plasma excitation during the etch process.

Abstract translation: 描述了从图案化异质结构中选择性地干蚀刻硅的方法。 该方法可选地包括在远程等离子体蚀刻之前的等离子体处理。 等离子体工艺可以使用偏置等离子体来处理一些晶体硅（例如多晶硅或单晶硅）以形成非晶硅。 随后，使用含氢前体形成远程等离子体以形成等离子体流出物。 等离子体流出物流入衬底处理区域以从图案化衬底中蚀刻非晶硅。 通过实施偏压等离子体处理，尽管在蚀刻过程中等离子体激发的远端性质，但是通常的各向同性蚀刻可以转化为定向（各向异性）蚀刻。

公开(公告)号：US20150279687A1

公开(公告)日：2015-10-01

申请号：US14231180

申请日：2014-03-31

Applicant: Applied Materials, Inc.

Inventor： Jun Xue ,  Chentsau Ying ,  Srinivas D. Nemani

IPC: H01L21/311 ,  H01L21/3065

CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01L21/3065 ,  H01L21/32137 ,  H01L29/66545

Abstract: A method of selectively dry etching silicon from patterned heterogeneous structures is described. The method optionally includes a plasma process prior to a remote plasma etch. The plasma process may use a biased plasma to treat some crystalline silicon (e.g. polysilicon or single crystal silicon) to form amorphous silicon. Subsequently, a remote plasma is formed using a hydrogen-containing precursor to form plasma effluents. The plasma effluents are passed into the substrate processing region to etch the amorphous silicon from the patterned substrate. By implementing biased plasma processes, the normally isotropic etch may be transformed into a directional (anisotropic) etch despite the remote nature of the plasma excitation during the etch process.

Abstract translation: 描述了从图案化异质结构中选择性地干蚀刻硅的方法。 该方法可选地包括在远程等离子体蚀刻之前的等离子体处理。 等离子体工艺可以使用偏置等离子体来处理一些晶体硅（例如多晶硅或单晶硅）以形成非晶硅。 随后，使用含氢前体形成远程等离子体以形成等离子体流出物。 等离子体流出物流入衬底处理区域以从图案化衬底中蚀刻非晶硅。 通过实施偏压等离子体处理，尽管在蚀刻过程中等离子体激发的远端性质，但是通常的各向同性蚀刻可以转化为定向（各向异性）蚀刻。